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@@ -27,7 +27,7 @@ Also, the computing system has its own decoupling capacitor (C2) to stabilize op
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Recent studies increasingly explore 32-bit architectures for the computing system~\cite{shihIntermittent2024,wuIntOS2024,kimRapid2024,akhunovEnabling2023,kimLACT2024,kimLivenessAware2023,parkEnergyHarvestingAware2023,kortbeekWARio2022,khanDaCapo2023,barjamiIntermittent2024,songTaDA2024}, as emerging applications on intermittent systems, such as Deep Neural Networks (DNNs)~\cite{houTale2024,yenKeep2023,khanDaCapo2023,gobieskiIntelligence2019,islamEnabling2022,kangMore2022,leeNeuro2019,islamZygarde2020,custodeFastInf2024,barjamiIntermittent2024,songTaDA2024}, demand greater computational capabilities~\cite{bakarProtean2023a,carontiFinegrained2023}.
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% Emerging intermittent applications demand increasing computing capability~\cite{bakarProtean2023a} due to computat
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-In this context, we employ a custom-built board featuring a 32-bit ARM Cortex-M33 processor (operating at 16Mhz) with 512KB of Ferroelectric RAM (FRAM) as a reference system.
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+In this context, we employ a custom-built board featuring a 32-bit ARM Cortex-M33 processor (operating at 16Mhz) with 1MB of Ferroelectric RAM (FRAM, Infineon FM22L16) as a reference system.
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A TI BQ25570 based board is used for the power management system.
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We empirically select 22uF and 220uF capacitors for C1 and C2, respectively, as these are the minimum capacitor sizes for stable checkpoint and recovery.
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Sec.~\ref{sec:other_architectures} evaluates generality of our model in different architectures, such as systems with Magnetic RAM (MRAM) and a 16-bit core (e.g., MSP430).
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@@ -215,12 +215,32 @@ Fig.~\ref{fig:fram_drror}: FRAM error.
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\subsection{Sensitivity to Architectural Designs}
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\label{sec:other_architectures}
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-Finally, we evaluate our model against two different architectural setups: MSP430 and Cortex-M33 with MRAM.
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-MSP430 has less computational capability than Cortex-M33 cores.
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-But it is a most popular platform for intermittent system researches, since it is a low-power system having on-chip FRAM.
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-We used MSP430FR5994 evaluation board, having 10uF of onboard decap.
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-For the second setup, we put MRAM to our evaluation platform instead of FRAM.
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-Core frequencies, capacitance of power management system, input power targeting about 50 ms execution.
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+% Please add the following required packages to your document preamble:
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+% \usepackage{booktabs}
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+% \usepackage{multirow}
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+% \usepackage{graphicx}
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+\begin{table}[]
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+ \centering
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+ \caption{Architectures}
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+ \label{tab:architectures}
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+ \renewcommand{\arraystretch}{0.9} % Reduce vertical spacing
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+ \setlength{\tabcolsep}{3pt} % Reduce horizontal spacing
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+ \resizebox{\columnwidth}{!}{%
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+ \begin{tabular}{@{}cccccccc@{}}
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+ \toprule
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+ \multirow{2}{*}{} & \multirow{2.5}{*}{Core} & \multirow{2.5}{*}{\begin{tabular}[c]{@{}c@{}}Core\\ Freq.\end{tabular}} & \multicolumn{3}{c}{Capacitance (uF)} & \multirow{2.5}{*}{Current} & \multirow{2.5}{*}{Memory} \\ \cmidrule(lr){4-6}
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+ & & & C1 & C2 & Storage & & \\ \midrule
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+ MRAM & STM32L5 & 16MHz & 22 & 220 & 1,320 & 3mA & \begin{tabular}[c]{@{}c@{}}MRAM\\ (off-chip)\end{tabular} \\
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+ MSP430 & MSP430FR5994 & 8MHz & 22 & 10 & 40 & 100uA & \begin{tabular}[c]{@{}c@{}}FRAM\\ (on-chip)\end{tabular} \\ \bottomrule
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+ \end{tabular}%
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+ }
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+ \end{table}
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+
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+We evaluate our model against two different architectural setups.
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+First, Cortex-M33 core equipped with MRAM (Everspin MR5A16ACYS35) is evaluated as MRAM is also gaining attention as a next generation NVM.
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+Second target is MSP430, which has been most popular platform in intermittent system research.
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+For both systems, we set architectural parameters to make operation time around 50ms.
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+Detailed parameters are shown in Table~\ref{tab:architectures}.
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\begin{figure}
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\centering
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