Update on local

sections/OurApproach.tex

@@ -11,6 +11,7 @@
 \end{figure}
 
 \subsection{Use Vdd for Checkpoint Trigger}
+\label{sec:use_vdd}
 
 \begin{figure}
     \centering

sections/OurModel.tex

@@ -193,7 +193,8 @@ However, the majority of execution may happen after the power-off threshold at s
 Being aware of this is important to software designers since the peripherals and analog components may function differently at sub-normal voltage.
 
 The two most critical examples are Analog-Digital Converters (ADCs) and external NVMs.
-They play an important role in checkpointing, since ADCs are often used to estimate power-off time by reading the capacitor voltage and NVMs have to save the checkpoint data safely.
+They play an important role in checkpointing and are likely used at sub-normal voltage, since ADCs are often used to estimate power-off time by reading the capacitor voltage and NVMs have to save the checkpoint data safely.
+Incorrect execution of these components may lead to unsafe or incomplete checkpoint executions.
 
 \begin{figure}
     \centering
@@ -212,8 +213,11 @@ They play an important role in checkpointing, since ADCs are often used to estim
     \label{fig:adc_and_fram_error}
 \end{figure}
 
-Fig.~\ref{fig:adc_error}: ADC error.
-Fig.~\ref{fig:fram_drror}: FRAM error.
+Fig.~\ref{fig:adc_error} shows the behavior of ADCs in sub-normal voltage.
+As STM32L5 uses Vdd as a reference voltage of ADC, accessing ADC at sub-normal Vdd results in increased values.
+Fig.~\ref{fig:fram_drror} shows the error rate of FRAM at different voltages.
+In our case, FRAM cannot operate correctly when the supply voltage is below 2.4V.
+When the system is configured to execute until the lowest MCU operation voltage, which is default in STM32L5 and cannot be changed in MSP430, executing checkpoint below the safe voltage results in corrupting checkpoint data.
 
 \subsection{Sensitivity to Architectural Designs}
 \label{sec:other_architectures}
@@ -224,7 +228,7 @@ Fig.~\ref{fig:fram_drror}: FRAM error.
 % \usepackage{graphicx}
 \begin{table}[]
     \centering
-    \caption{Architectures}
+    \caption{Architectures for generality evaluation}
     \label{tab:architectures}
     \renewcommand{\arraystretch}{0.9} % Reduce vertical spacing
     \setlength{\tabcolsep}{3pt} % Reduce horizontal spacing
@@ -239,11 +243,12 @@ Fig.~\ref{fig:fram_drror}: FRAM error.
     }
     \end{table}
 
-We evaluate our model against two different architectural setups.
-First, Cortex-M33 core equipped with MRAM (Everspin MR5A16ACYS35) is evaluated as MRAM is also gaining attention as a next generation NVM.
-Second target is MSP430, which has been most popular platform in intermittent system research.
+To evaluate the generality of our model, we employ two additional architectural setups.
+Table~\ref{tab:architectures} shows the detailed parameters of them.
+A1 is a same setup with the reference system but having MRAM (Everspin MR5A16ACYS35).
+This setup is evaluated as MRAM is also gaining attention as a next generation NVM.
+Second target is MSP430, which has been most popular 16-bit platform in intermittent system research.
 For both systems, we set architectural parameters to make operation time around 50ms.
-Detailed parameters are shown in Table~\ref{tab:architectures}.
 
 \begin{figure}
     \centering
@@ -253,4 +258,10 @@ Detailed parameters are shown in Table~\ref{tab:architectures}.
 \end{figure}
 
 Fig.~\ref{fig:other_architectures} shows the results in different power-off voltage.
-The bar in the left shows the energy breakdown in one power cycle, and the one in the right represents the ratio of the execution time operated in sub-voltage.
+The bar in the left side shows the energy breakdown in one power cycle, and the one in the right side represents the ratio of the execution time operated at sub-voltage.
+The most noticeable difference is ratio of energy consumed for ramp-up and init.
+While A1 consumes xx\% power at this stage on average, A2 consumes only xx\%.
+This is because A1 shows larger leakage current due to external MRAM, which consumes more current than FRAM in our case.
+However, both architectures show high sub-voltage execution rates, up to xx\% in A2.
+In addition, discharged energy takes considerable portion both in A1 (xx\%) A2 (xx\%) at 3.3V configuration, which represents the techniques based on the traditional model.
+In summary, the evaluation reveals that the buffering effect of system's capacitance and its implications are general in other systems.