Update on local

sections/OurModel.tex

@@ -192,8 +192,9 @@ The traditional model makes the software designers assume the system is executed
 However, the majority of execution may happen after the power-off threshold at sub-normal voltage (\textbf{O3}), as discussed in Sec.~\ref{sec:predicting_power_failures}.
 Being aware of this is important to software designers since the peripherals and analog components may function differently at sub-normal voltage.
 
-The two most critical examples are Analog-Digital Converters (ADCs) and external NVMs.
-They play an important role in checkpointing and are likely used at sub-normal voltage, since ADCs are often used to estimate power-off time by reading the capacitor voltage and NVMs have to save the checkpoint data safely.
+The two most relevant examples are Analog-Digital Converters (ADCs) and external NVMs.
+They play an important role in checkpointing, since ADCs are often used to estimate power-off time by reading the capacitor voltage and NVM is the checkpoint storage itself.
+At the same time, they are likely executed at sub-normal voltage as checkpoint is executed just before the power-off.
 Incorrect execution of these components may lead to unsafe or incomplete checkpoint executions.
 
 \begin{figure}
@@ -214,10 +215,16 @@ Incorrect execution of these components may lead to unsafe or incomplete checkpo
 \end{figure}
 
 Fig.~\ref{fig:adc_error} shows the behavior of ADCs in sub-normal voltage.
-As STM32L5 uses Vdd as a reference voltage of ADC, accessing ADC at sub-normal Vdd results in increased values.
-Fig.~\ref{fig:fram_drror} shows the error rate of FRAM at different voltages.
-In our case, FRAM cannot operate correctly when the supply voltage is below 2.4V.
-When the system is configured to execute until the lowest MCU operation voltage, which is default in STM32L5 and cannot be changed in MSP430, executing checkpoint below the safe voltage results in corrupting checkpoint data.
+ADC quantizes the input analog voltage into the range of discrete $n$ values from 0 to $V_{ref}$, where $n$ is a resolution and $V_{ref}$ is a reference voltage.  
+As STM32L5 uses Vdd as reference voltage, accessing ADC during sub-normal voltage operation results in inconsistent results.
+As shown in the figure, it returns larger values than the measurements since the range ADC can represent is decreased as Vdd decreases.
+As a result, during sub-normal voltage operation, the system may believe there is sufficient energy from the ADC results and decide not to execute checkpoint.
+
+Also, some peripherals may not work below certain voltage.
+Fig.~\ref{fig:fram_drror} presents the error rate of FRAM in the reference system at different voltages, showing FRAM cannot operate correctly when the voltage is below 2.4V.
+Since the system operates until it reaches the lowest MCU operation voltage (e.g., 1.7V), software designers should guarantee that peripherals are accessed at safe voltage.
+In our reference system, failing to this may result in corrupted or incomplete checkpointing.
+In Sec.~\ref{sec:design_guidelines}, we propose two techniques that can safely estimate the power-off time under sub-normal voltage.
 
 \subsection{Sensitivity to Architectural Designs}
 \label{sec:other_architectures}
@@ -245,8 +252,8 @@ When the system is configured to execute until the lowest MCU operation voltage,
 
 To evaluate the generality of our model, we employ two additional architectural setups.
 Table~\ref{tab:architectures} shows the detailed parameters of them.
-A1 is a same setup with the reference system but having MRAM (Everspin MR5A16ACYS35).
-This setup is evaluated as MRAM is also gaining attention as a next generation NVM.
+A1 is the same setup with the reference system but equips MRAM (Everspin MR5A16ACYS35) instead of FRAM.
+This setup is evaluated as MRAM is also gaining attention as a next generation NVM~\cite{akhunovEnabling2023,bakarProtean2023a,dewinkelIntermittentlypowered2022,wuIntOS2024}.
 Second target is MSP430, which has been most popular 16-bit platform in intermittent system research.
 For both systems, we set architectural parameters to make operation time around 50ms.