Update on local

sections/OurApproach.tex

@@ -6,16 +6,19 @@
 
 \begin{figure}
     \centering
-    \includegraphics[width=\linewidth]{figs/plot_expr_10_cropped.pdf}
-    \caption{Caption (JIT).}
-    % \label{fig:detailed_execution_model}
-\end{figure}
-
-\begin{figure}
-    \centering
-    \includegraphics[width=\linewidth]{figs/plot_expr_11_cropped.pdf}
-    \caption{Caption (static).}
-    % \label{fig:detailed_execution_model}
+    \begin{subfigure}{\linewidth}
+        \includegraphics[width=\textwidth]{figs/plot_expr_10_cropped.pdf}
+        \caption{Dynamic checkpointing (JIT).}
+        % \label{fig:eval_voltage_trace}
+        \vspace{7pt}
+    \end{subfigure}
+    \begin{subfigure}{\linewidth}
+        \includegraphics[width=\textwidth]{figs/plot_expr_11_cropped.pdf}
+        \caption{Static checkpointing.}
+        % \label{fig:eval_adaptivenss_finished_tasks}
+    \end{subfigure}
+    \caption{Impact of precise checkpoint timings to the end-to-end execution times.}
+    % \label{fig:sub_voltage_execution}
 \end{figure}
 
 \subsection{Design Checkpoint Techniques for Sufficient Power Duration}

sections/OurModel.tex

@@ -24,12 +24,12 @@ This setup includes two notable decoupling capacitors that affect the execution
 The first one (C1 in the figure) is placed at the power management system as voltage regulators require a capacitor larger than the device-specific minimum capacitance for stable operation.
 Also, the computing system has its own decoupling capacitor (C2) to stabilize operating voltage.
 
-Recent studies increasingly consider use of 32-bit architectures for the computation system~\cite{shihIntermittent2024,wuIntOS2024,kimRapid2024,akhunovEnabling2023,kimLACT2024,kimLivenessAware2023,parkEnergyHarvestingAware2023,kortbeekWARio2022,khanDaCapo2023}, as emerging applications on intermittent systems, such as DNNs, demand more computing capability~\cite{bakarProtean2023a,carontiFinegrained2023}.
+Recent studies increasingly consider use of 32-bit architectures for the computing system~\cite{shihIntermittent2024,wuIntOS2024,kimRapid2024,akhunovEnabling2023,kimLACT2024,kimLivenessAware2023,parkEnergyHarvestingAware2023,kortbeekWARio2022,khanDaCapo2023}, as emerging applications on intermittent systems, such as DNNs~\cite{houTale2024,yenKeep2023,khanDaCapo2023,gobieskiIntelligence2019,islamEnabling2022a,kangMore2022,leeNeuro2019,islamZygarde2020}, demand more computing capability~\cite{bakarProtean2023a,carontiFinegrained2023}.
 % Emerging intermittent applications demand increasing computing capability~\cite{bakarProtean2023a} due to computat
-To this end, we use a custom-built board equipped with an ARM Cortex-M33 running at 16MHz and 512KB of FRAM as a reference system for validation and evaluation.
+To this end, we use a custom-built board equipped with an ARM Cortex-M33 (operating at 16Mhz) and 512KB of FRAM as a reference system in this section.
 For power management system, we use TI BQ25570 based system.
-We empirically choose XXuF and 220uF capacitors for C1 and C2, respectively, as minimum capacitor sizes for stable execution of checkpoint and recovery.
-Sec.~\ref{sec:other_architectures} evaluates our model in different architectures, such as systems with MRAM and 16-bit core.
+We empirically choose XXuF and 220uF capacitors for C1 and C2, respectively, as these are the minimum capacitor sizes for stable execution of checkpoint and recovery.
+For generality, Sec.~\ref{sec:other_architectures} evaluates our model in different architectures, such as systems with MRAM and 16-bit core.
 
 % In this work, our goal is to model the buffering effects of these capacitors and evaluate their implications on software designs.
 % (Recent studies present the need for better computing capability~\cite{bakarProtean2023a})
@@ -58,7 +58,7 @@ Sec.~\ref{sec:other_architectures} evaluates our model in different architecture
 \end{figure}
 
 Fig.~\ref{fig:execution_trace} shows the voltage trace of the energy storage and the Vdd of the computing system.
-A 470uF capacitor is used for the energy storage to generate execution of about 48 ms under 1.5mA current supply.
+A 470uF capacitor is used for the energy storage to generate execution of about 50 ms under 1.5mA current supply.
 Fig.~\ref{fig:execution_trace_one_cycle} shows the trace during one power cycle, and Fig.~\ref{fig:execution_trace_detailed} presents the first execution cycle in more detail.
 
 Three key observations that affect software designer's decision.
@@ -125,13 +125,19 @@ In 470uF case, the actual energy efficiency (Execution) and the expectation from
         % \label{fig:eval_adaptivenss_finished_tasks}
     \end{subfigure}
     \caption{Ratio of sub-voltage operations in total execution time.}
-    % \label{fig:}
+    \label{fig:sub_voltage_execution}
 \end{figure}
 
 According to the traditional model, the system states should be saved to NVM before power-off threshold.
-Our model shows that the system may operate after this point using the energy stored in the decaps (\textbf{O2}). 
+Our model shows that the system may operate after this point using the energy stored in the decoupling capacitors (\textbf{O2}). 
 As a result, the energy storage voltage is not a good approximate of the remaining time that system can execute.
 
+Modern MCUs can operate on wide range of operating voltages. 
+Our case: 1.7V to 3.6V.
+
+Fig.~\ref{fig:sub_voltage_execution} shows the ratio of sub-voltage executions over total execution times.
+The x-axis shows the different capacitor sizes and the colors represent various power-off voltages.
+
 \subsection{Impact of Sub-normal Voltage Execution}
 
 The traditional model makes the software designers assume the system is executed under stable voltage.
@@ -145,18 +151,21 @@ The two most critical examples are Analog-Digital Converter (ADC) and external m
     \begin{subfigure}{0.45\linewidth}
         \includegraphics[width=\textwidth]{figs/plot_expr_2_cropped.pdf}
         \caption{Trace of one power cycle.}
-        % \label{fig:eval_voltage_trace}
+        \label{fig:adc_error}
     \end{subfigure}
     \hfill
     \begin{subfigure}{0.52\linewidth}
         \includegraphics[width=\textwidth]{figs/plot_expr_3_cropped.pdf}
         \caption{Detailed trace.}
-        % \label{fig:eval_adaptivenss_finished_tasks}
+        \label{fig:fram_drror}
     \end{subfigure}
     \caption{Voltage of the capacitor and Vdd, sampled 470uF and 1.5mA.}
-    % \label{fig:}
+    \label{fig:adc_and_fram_error}
 \end{figure}
 
+Fig.~\ref{fig:adc_error}: ADC error.
+Fig.~\ref{fig:fram_drror}: FRAM error.
+
 \subsection{Sensitivity to Architectural Designs}
 \label{sec:other_architectures}
 

sections/RelatedWork.tex

@@ -1,6 +1,6 @@
 \section{Related Work}
 
-Techniques to find the best hardware configurations (model approaches).
+Techniques to find the best hardware configurations (model approaches~\cite{kimRapid2024,houTale2024,erataETAP2023,ghasemiPES2023,sanmiguelEH2018a,sanmiguelEH2018}).
 Tradeoff of capacitor size and forward progress~\cite{zhanExploring2022}.
 These works do not consider discharge of decoupling capacitor.