Update on local

IEEE-conference-template-062824.tex

@@ -20,7 +20,8 @@
 \begin{document}
 
 \title{Intermittent Systems at Small Scale: Execution Model and Design Guidelines \\
-\thanks{This work was supported by IITP grant funded by the Korea government (MSIT) (No.2021-0-00360, Development of Core Technology for Autonomous Energy-driven Computing System SW in Power-instable Environment).}
+% \thanks{This work was supported by IITP grant funded by the Korea government (MSIT) (No.2021-0-00360, Development of Core Technology for Autonomous Energy-driven Computing System SW in Power-instable Environment).}
+\thanks{This work was supported by IITP grant funded by the Korea government (MSIT) (No.2021-0-00360).}
 }
 
 \author{\IEEEauthorblockN{Youngbin Kim and Yoojin Lim}
@@ -32,13 +33,17 @@ Electronics and Telecommunications Research Institute (ETRI), Daejeon, Republic
 \maketitle
 
 \begin{abstract}
-    Intermittent systems execute long-running tasks in environments with frequent power failures, using small capacitors as energy storages.
-    Software designers rely on execution models that abstract hardware-level operations and describe how intermittent systems work.  
-    % When designing such systems, software designers rely on execution models that abstract operations at the hardware level and describe how intermittent systems work.  
-    However, as recent techniques target very short operation times with smaller energy storages, traditional models are failing to provide precise abstractions of the actual behavior.
-    In this paper, we propose a more accurate execution model that accounts for the buffering effects of a system's inherent capacitance, which is a major source of inconsistency in traditional models.
-    Our evaluation shows that systems designed upon the traditional model can be up to 5.62x less power efficient than expected and may lead to unsafe checkpoint execution.
-    Additionally, based on our model, we present design guidelines for small-scale intermittent systems, which improve the end-to-end latency of applications by 2.85x in dynamic and 3.04x in static checkpoint schemes, without any extra overhead. 
+    % Intermittent systems execute long-running tasks in environments with frequent power failures, using small capacitors as energy storages.
+    % Software designers rely on execution models that abstract hardware-level operations and describe how intermittent systems work.  
+    % However, as recent techniques target very short operation times with smaller energy storages, traditional models are failing to provide precise abstractions of the actual behavior.
+    % In this paper, we propose a more accurate execution model that accounts for the buffering effects of a system's inherent capacitance, which is a major source of inconsistency in traditional models.
+    % Our evaluation shows that systems designed upon the traditional model can be up to 5.62x less power efficient than expected and may lead to unsafe checkpoint execution.
+    % Additionally, based on our model, we present design guidelines for small-scale intermittent systems, which improve the end-to-end latency of applications by 2.85x in dynamic and 3.04x in static checkpoint schemes, without any extra overhead. 
+    Intermittent systems require software support to execute tasks amid frequent power failures. 
+    In designing such techniques, software designers rely on execution models that abstract hardware-level operations. 
+    In this paper, we propose an execution model that more accurately describes emerging intermittent systems with small energy storage. 
+    Our evaluation shows show that systems designed based on the traditional models can be up to 5.62x less power-efficient than expected and may result in unsafe checkpoint operations. 
+    Our design guidelines enhance the performance of existing static and dynamic checkpoint techniques by 3.04x and 2.85x on average, respectively.
 \end{abstract}
 
 \begin{IEEEkeywords}

sections/OurApproach.tex

@@ -97,6 +97,35 @@ Since the both setups only modify the method to detect imminent power failures a
 Furthermore, the proposed setups can reduce the complexity of the system, as they eliminate the need for communication (e.g., interrupt or access to $V_{ES}$) between the energy storage system and the computing system.
 
 % \subsection{Checkpoint Techniques and Evaluation Methods}
-% % \subsection{Design Checkpoint Techniques for Sufficient Power Duration}
+\subsection{On Selecting Hardware Components}
+
+Our model helps designers to select efficient hardware components in various aspects.
+For example, it implies that operating voltage of peripherals (e.g., external NVMs) is a critical design parameter, often more important than their latency.
+% We evaluate this tradeoff by simulating an external FRAM having faster access latency but smaller operating voltage.
+We evaluate this tradeoff by simulating two FRAM configurations, F1 and F2, in our reference system.
+F1 represents slower setup operating until 2.5V; we double the software-configurable wait time for FRAM accesses for this setup.
+In F2, the fastest FRAM access parameters are used but the system stops operating at 2.8V.
+
+\begin{figure}
+    \centering
+    \includegraphics[width=\linewidth]{figs/plot_expr_12_cropped.pdf}
+    \caption{Impact of peripheral operating voltage.}
+    \label{fig:expr_peripheral_voltage}
+\end{figure}
+
+Fig.~\ref{fig:expr_peripheral_voltage} presents the results.
+It shows that operating voltage should considered, which can be ignored in the traditional execution model.
+
+Finally, our model highlights advantages of using smaller decoupling capacitors.
+Using larger buffers not only increases the ratio of sub-normal voltage operations but also increases the amount of discharged energy during power-offs.
+Indeed, we observe our reference system requires xx\% and xx\% longer time on average for execution of the benchmarks, when xxuF and xxuF decoupling capacitors are used, compared to our design of 220uF.
+As a result, it is a good design practice to use the smallest decoupling capacitors for efficiency of intermittent systems.
+
+% \begin{figure}
+%     \centering
+%     \includegraphics[width=\linewidth]{figs/plot_expr_12_cropped.pdf}
+%     \caption{Execution times with varying decoupling capacitors.}
+%     % \label{fig:expr_checkpoint_voltages}
+% \end{figure}
 
 % Power failure injection (soft reset)~\cite{wuIntOS2024,yildizEfficient2023}.

sections/OurModel.tex

@@ -26,7 +26,7 @@ The first one (C1 in the figure) is located within the power management system a
 The second capacitor (C2) is part of the computing system and it stabilizes the operating voltage against sudden current draw.
 
 Recent studies have increasingly explored 32-bit architectures for computing systems~\cite{shihIntermittent2024,wuIntOS2024,kimRapid2024,akhunovEnabling2023,kimLACT2024,kimLivenessAware2023,parkEnergyHarvestingAware2023,kortbeekWARio2022,khanDaCapo2023,barjamiIntermittent2024,songTaDA2024}, as emerging applications on intermittent systems, such as Deep Neural Networks (DNNs)~\cite{houTale2024,yenKeep2023,khanDaCapo2023,gobieskiIntelligence2019,islamEnabling2022,kangMore2022,leeNeuro2019,islamZygarde2020,custodeFastInf2024,barjamiIntermittent2024,songTaDA2024}, demand greater computational capabilities~\cite{bakarProtean2023a,carontiFinegrained2023}.
-In this context, we employ a custom-built board featuring a 32-bit ARM Cortex-M33 processor (STM32L5, operating at 16Mhz) with 512KB of Ferroelectric RAM (FRAM) as our reference system.
+In this context, we employ a custom-built board featuring a 32-bit ARM Cortex-M33 processor (STM32L5, operating at 16Mhz) with 512KB of Ferroelectric RAM (FRAM, Infineon FM22L16) as our reference system.
 For the power management system, we use a TI BQ25570-based board configured with $V_h$ = 4.9V and $V_l$ = 3.4V.
 % For the power management system, we use a TI BQ25570-based board with power-on and power-off thresholds of 4.9 V and 3.4 V, respectively.
 % A TI BQ25570 based board is used for the power management system, with power-on and off thresholds of 4.9V and 3.4V, respectively.
@@ -255,7 +255,7 @@ Failing to do so can result in corrupted sensor data or unsafe checkpointing.
     \begin{tabular}{@{}cccccccc@{}}
     \toprule
     \multirow{2}{*}{} & \multirow{2.5}{*}{Core} & \multirow{2.5}{*}{\begin{tabular}[c]{@{}c@{}}Core\\ Freq.\end{tabular}} & \multicolumn{3}{c}{Capacitance (uF)} & \multirow{2.5}{*}{Current} & \multirow{2.5}{*}{Memory}                                   \\ \cmidrule(lr){4-6}
-                      &                       &                                                                       & C1       & C2        & Storage       &                          &                                                           \\ \midrule
+                      &                       &                                                                       & C1       & C2        & C\textsubscript{ES}       &                          &                                                           \\ \midrule
     A1              & STM32L5               & 16MHz                                                                 & 22       & 220       & 1,320         & 3mA                      & \begin{tabular}[c]{@{}c@{}}MRAM\\ (off-chip)\end{tabular} \\
     A2            & MSP430FR5994          & 8MHz                                                                  & 22       & 10        & 40            & 100uA                    & \begin{tabular}[c]{@{}c@{}}FRAM\\ (on-chip)\end{tabular}  \\ \bottomrule
     \end{tabular}%