Update on local

IEEE-conference-template-062824.tex

@@ -27,7 +27,7 @@
 
 \title{Intermittent Systems at Small Scale: Execution Model and Design Guidelines \\
 % \thanks{This work was supported by IITP grant funded by the Korea government (MSIT) (No.2021-0-00360, Development of Core Technology for Autonomous Energy-driven Computing System SW in Power-instable Environment).}
-% \thanks{This work was supported by IITP grant funded by the Korea government (MSIT) (No.2021-0-00360).}
+\thanks{This work was supported by IITP grant funded by the Korea government (MSIT) (No.2021-0-00360).}
 }
 
 \author{\IEEEauthorblockN{Youngbin Kim and Yoojin Lim}

sections/Introduction.tex

@@ -36,8 +36,8 @@ This factor has been overlooked in the traditional model, as the inherent capaci
 
 Decoupling capacitors are on-board capacitors that act as energy buffers.
 They are mandatory since the buffered energy prevent transient voltage drop when the system suddenly draws a large current, such as during checkpointing (Sec.~\ref{sec:system_description}).
-However, at the same time, their buffering effects introduce discrepancies between the execution model and the actual system behavior.
-For example, during power-on, decoupling capacitors are rapidly charged using the energy in the storage, making capacitor voltage an unreliable estimate of available energy.
+However, their buffering effects also introduce discrepancies between the execution model and actual behavior.
+For example, during power-on, they rapidly charge from the energy storage, making capacitor voltage an unreliable estimate of available energy.
 This buffered energy also allows the system operate for a while at sub-normal voltages after the power supply is stopped.
 Additionally, between power cycles, decoupling capacitors discharge due to the resistance of the system, considerably lowering the power efficiency.
 In systems with smaller capacitors, these effects dominate the behaviors that are modeled in the traditional execution model.
@@ -60,6 +60,7 @@ Consequently, highly efficient checkpoint techniques according to the traditiona
 In this paper, we propose a new execution model for intermittent systems which accounts for the buffering effects of decoupling capacitors.
 In Sec.~\ref{sec:detailed_execution_model}, we demonstrate that understanding this model is critical for software designers:
 intermittent systems designed upon the traditional model can be up to 5.62x more energy-inefficient than expected and may fail to predict power-off timings accurately, leading to unsafe checkpointing. 
-In Sec.~\ref{sec:design_guidelines}, we propose design guidelines to implement efficient and safe intermittent systems with small energy storages, leveraging insights from our model.
-Our guidelines include accurate power failure prediction methods that improve end-to-end execution latencies by 3.04x in static and 2.86x in dynamic checkpointing schemes on average, without incurring additional overhead.
+In Sec.~\ref{sec:design_guidelines}, we present design guidelines to implement efficient intermittent systems with small energy storages, leveraging insights from our model.
+Our guidelines include designs which improve end-to-end execution latencies by 3.04x in static and 2.86x in dynamic checkpointing schemes on average, without incurring additional overhead.
+% Our guidelines include accurate power failure prediction methods that improve end-to-end execution latencies by 3.04x in static and 2.86x in dynamic checkpointing schemes on average, without incurring additional overhead.
 % Our power failure prediction methods improve end-to-end execution latencies by 3.04x in static and 2.86x in dynamic checkpointing schemes on average, without incurring additional overhead.

sections/OurModel.tex

@@ -17,13 +17,15 @@ Finally, in Sec.~\ref{sec:other_architectures}, we evaluate the effectiveness of
     \label{fig:hardware_setup}
 \end{figure}
 
-A typical intermittent system consists of two main components: a power management system and a computing system, as illustrated in Fig.~\ref{fig:hardware_setup}.
-The power management system is responsible for accumulating the incoming energy into storage ($C_{ES}$) and providing a stable-voltage current to the computing system.
-The computing system equips NVMs along with the MCU and peripherals, and utilize the NVMs for state retention between power failures.
+A typical intermittent system consists of two main components: a power management system and a computing system, as shown in Fig.~\ref{fig:hardware_setup}.
+The power management system collects incoming energy into storage ($C_{ES}$) and supplies a stable-voltage current to the computing system.
+% The power management system is responsible for accumulating the incoming energy into storage ($C_{ES}$) and providing a stable-voltage current to the computing system.
+The computing system equips NVMs along with an MCU and peripherals, and utilize the NVMs for state retention between power failures.
 
 This setup includes two notable decoupling capacitors that affect the execution model of intermittent systems.
-The first one (C1 in the figure) is located within the power management system as voltage regulators require a capacitor larger than the device-specific minimum to ensure stable operation.
-The second capacitor (C2) is part of the computing system and it stabilizes the operating voltage against sudden current draw.
+% The first one (C1 in the figure) is located within the power management system, as voltage regulators require a capacitance above the device-specific minimum for stable operation.
+The first one (C1) is located in the power management system, required by voltage regulators to ensure stable operation.
+The second capacitor (C2) is part of the computing system and used to stabilize the operating voltage against sudden current draw.
 
 Recent studies have increasingly explored 32-bit architectures for computing systems~\cite{shihIntermittent2024,wuIntOS2024,kimRapid2024,akhunovEnabling2023,kimLACT2024,kimLivenessAware2023,parkEnergyHarvestingAware2023,kortbeekWARio2022,khanDaCapo2023,barjamiIntermittent2024,songTaDA2024}, as emerging applications on intermittent systems, such as Deep Neural Networks (DNNs)~\cite{houTale2024,yenKeep2023,khanDaCapo2023,gobieskiIntelligence2019,islamEnabling2022,kangMore2022,leeNeuro2019,islamZygarde2020,custodeFastInf2024,barjamiIntermittent2024,songTaDA2024}, demand greater computational capabilities~\cite{bakarProtean2023a,carontiFinegrained2023}.
 In this context, we employ a custom-built board featuring a 32-bit ARM Cortex-M33 processor (STM32L5, operating at 16Mhz) with 512KB of Ferroelectric RAM (FRAM, Infineon FM22L16) as our reference system.
@@ -62,7 +64,7 @@ Sec.~\ref{sec:other_architectures} evaluates the generality of our model across
 
 To derive a general execution model with the effects of decoupling capacitors, we first present a sample measurement from our reference system.
 In this paper, we denote the voltage of the energy storage $C_{ES}$ as $V_{ES}$ and the MCU operating voltage as $V_{dd}$.
-To achieve an operation time of 50 ms under 1.5 mA current supply, we use a 470 uF capacitor for $C_{ES}$.
+To achieve an operation time of 50 ms under 1.5mA current supply, we use a 470uF capacitor for $C_{ES}$.
 Fig.~\ref{fig:execution_trace_one_cycle} illustrates the voltage traces of $V_{ES}$ and $V_{dd}$ over a single power cycle.
 Note that $V_{dd}$ is maintained by decoupling capacitors once the power supply from the power management system stops.
 The shaded areas represent the periods that system executes the application code.
@@ -73,8 +75,8 @@ Among them, we highlight three key observations that affect software design deci
 
 \begin{itemize}
     \item \textbf{O1}: The capacitor voltage ($V_{ES}$) drops rapidly to charge decoupling capacitors when the system wakes up ($t1$--$t2$).
-    \item \textbf{O2}: System operates at sub-normal voltage using decoupling capacitors, even after power supply stops ($t4$--$t5$).
-    \item \textbf{O3}: Decoupling capacitors discharge while the system is powered off (after $t5$, as shown in Fig.~\ref{fig:execution_trace_one_cycle}).
+    \item \textbf{O2}: System operates at sub-normal voltage using decoupling capacitors, even after power supply stops ($t3$--$t4$).
+    \item \textbf{O3}: Decoupling capacitors discharge while the system is powered off (after $t4$, as shown in Fig.~\ref{fig:execution_trace_one_cycle}).
 \end{itemize}
 
 \begin{figure}
@@ -94,7 +96,7 @@ Since the voltage of the decoupling capacitors decreases as they discharge, the
 % This voltage is known as Brown-Out Reset (BOR) voltage and is typically in a range of 1.7V to 2.5V in modern MCUs~\cite{}.
 Finally, until the next power-on event, the remaining energy in decoupling capacitors continues to discharge (\circled{5}).
 
-When designing intermittent systems, particularly those utilizing small capacitors, understanding the effects described by our model is critical.
+When designing intermittent systems, particularly those utilizing small capacitors, understanding the effects described by this model is critical.
 % When designing intermittent systems, particularly those utilizing small capacitors, it is important for software designers to have clear understanding of this model.
 In the following sections, we discuss impacts of our model to software design in more detail.
 
@@ -113,19 +115,20 @@ This indicates that much smaller energy may be used for the useful computation c
     \label{fig:power_distribution}
 \end{figure}
 
-Fig.~\ref{fig:power_distribution} shows the distribution of the energy consumption for each stage of operation within one power cycle, averaged over 50 executions, where 1 mA of input current is provided at 1.9V.
-The x-axis represents energy storage sizes and the line in the secondary axis represents the average operation times for application code.
+Fig.~\ref{fig:power_distribution} shows the distribution of the energy consumption for each stage of operation within one power cycle, averaged over 50 executions, where 1mA of input current is provided at 1.9V.
+The x-axis represents the size of $C_{ES}$ and the line in the secondary axis represents the average operation times for application code.
 The checkpoint is executed by the interrupt from the power management system~\cite{jayakumarQUICKRECALL2014,maengSupporting2019,balsamoHibernus2016,balsamoHibernus2015,kortbeekTimesensitive2020}, which is generated when $V_{ES}$ reaches $V_l$ (3.4V).
 Note that this is the most efficient point for checkpoint execution according to the traditional model (i.e., just before the poweroff).
 
 The results shows that significant energy is wasted in the decoupling capacitors.
-For example, in 470 uF case, 60.7\% of the energy is lost during the power-off duration (denoted as \emph{Discharged}), leaving only 13.1\% of the energy for computation.
-The discharging behavior can be modeled as an RC-discharging circuit (i.e., $q=CVe^{-\frac{t}{RC}}$), which exhibits an exponential discharge rate.
+For example, in 470uF case, 60.7\% of the energy is lost during the power-off duration (denoted as \emph{Discharged}), leaving only 13.1\% of the energy for computation.
+While the ratio of \emph{Discharged} decreases with larger $C_{ES}$, it remains substantial;
+for example, in the 1320uF case, 28.5\% of energy is discharged, which is still non-negligible.
+
+This is because the discharging behavior can be modeled as an RC-discharging circuit (i.e., $q=CVe^{-\frac{t}{RC}}$), which exhibits an exponential discharge rate.
 Indeed, 50\% of the energy is discharged within the first 161 ms in our measurements.
-Since recharging $C_{ES}$ takes xx secs even in 470 uF configuration, most of the buffered energy is lost before the next power-on, regardless of the capacitor size.
+Since recharging $C_{ES}$ takes 2.13 secs even in 470uF configuration, most of the buffered energy is lost before the next power-on, regardless of the size of $C_{ES}$.
 As a result, the energy loss ratio due to discharging is larger with smaller capacitors.
-While this ratio decreases with larger $C_{ES}$, it remains substantial;
-for example, in the 1320 uF case, 28.5\% of energy is discharged, which is still non-negligible.
 % The discharge rate decreases as the capacitor size increases, down to 28.5\% in 1320uF case, which is still not negligible.
 % The cost is more expensive when the capacitor size is small since the discharge rate follows the RC-discharging circuits.
 % While using smaller capacitors shortens the power-off durations, the discharging behavior penalizes them most since RC-discharging circuits discharge exponentially (in our case, 50\% of energy is discharged at the first 161 ms).
@@ -133,8 +136,8 @@ for example, in the 1320 uF case, 28.5\% of energy is discharged, which is still
 
 Another important observation is the error introduced by the traditional model.
 The traditional model expects both the energies, \emph{Execution} and \emph{Discharged}, are used for computation.
-This introduces huge errors, up to 5.62x in 470 uF setup, for example.
-In the same context, the traditional model predicts that using a 470 uF $C_{ES}$ instead of a 1320 uF would result in only 1.22x overhead in energy efficiency, while the actual difference is 4.71x.
+This introduces huge errors, up to 5.62x in 470uF setup, for example.
+In the same context, the traditional model predicts that using a 470uF capacitor for $C_{ES}$ instead of a 1320uF would result in only 1.22x overhead in energy efficiency, while the actual difference is 4.71x.
 % However, our model shows that the actual energy efficiency differs by xx\% in reality, brining xx\% error in the traditional model.
 This can significantly mislead system designers when they select capacitor sizes by considering tradeoffs between overall efficiency and reactiveness.
 In Sec.~\ref{sec:design_guidelines}, we explore strategies to minimize the inefficiencies caused by discharging when designing software techniques.
@@ -179,7 +182,7 @@ This makes $V_{ES}$ not a reliable indicator for the imminent power-off.
 % Modern MCUs can operate on wide range of operating voltages (e.g., from 1.7V to 3.6V for STM32L5 and MSP430).
 
 Fig.~\ref{fig:sub_voltage_execution} presents the ratio of the times executed under sub-normal voltages to the total execution times, averaged over 30 measurements.
-The x-axis represents capacitor sizes and the colors indicate the voltage levels at which the system stops operation.
+The x-axis represents the sizes of $C_{ES}$ and the colors indicate the voltage levels at which the system stops operation.
 We evaluate a range of stop voltages from 1.7V to 2.5V since not all components in the computing system may function at the lowest voltage level (Sec.~\ref{sec:sub_normal_execution}).
 Also, we examine two cases with input currents of 1mA (Fig.~\ref{fig:sub_voltage_execution_1mA}) and 3mA (Fig.~\ref{fig:sub_voltage_execution_3mA}), to assess the impact of input power.
 
@@ -190,10 +193,10 @@ However, at least 13.0\% of computations are operated at sub-normal voltages eve
 % Overall, the average sub-voltage operation ratio is xx\% for the configurations exhibiting less than 100 ms, which is the main focus of this paper. 
 
 These values can be directly translated to the inefficiencies of the systems based on the traditional model.
-For example, in the case of 470uF with 1mA input current, systems executing checkpoint at $V_l$ may operate 16.3 ms.
-However, the system could operate for an additional 29.4ms if the checkpoint is executed at 2.5V.
-At the next power-on, the decoupling capacitors discharge to similar voltage levels in both cases, as their discharge behavior follows an exponential curve (Sec.~\ref{sec:power_efficiency}).
-As a result, failing to utilize the available energy at sub-normal voltage introduces significant power efficiency overhead.
+For example, in the case of 470uF with a input current of 1mA, systems executing checkpoint at $V_l$ may operate 16.3 ms.
+However, the system could operate for an additional 29.4 ms if the checkpoint can be delayed until 2.5V.
+At the next power-on, the decoupling capacitors discharge to similar voltage levels in both cases, as discussed in Sec.~\ref{sec:power_efficiency}.
+As a result, failing to utilize the buffered energy at sub-normal voltages introduces significant power inefficiency.
 % Although early checkpoint execution may save some energy in decoupling capacitors, the saved energy is not preserved as discussed in Sec.~\ref{sec:power_efficiency}.
 In Sec.~\ref{sec:use_vdd_for_checkpoint}, we validate this aspect and propose methods to fully utilize the buffered energy.
 
@@ -206,7 +209,7 @@ Being aware of this is crucial to software designers since analog components and
 
 Two of the most relevant examples are Analog-Digital Converters (ADCs) and external NVMs.
 They play an important role in checkpointing: ADCs are commonly used to determine when to execute a checkpoint by reading $V_{ES}$ and NVM serves as the storage for the checkpoints.
-At the same time, they are likely to operate at sub-normal voltages, as checkpoint executions typically happen just before the power-off.
+% At the same time, they are likely to operate at sub-normal voltages, as checkpoint executions typically happen just before the power-off.
 % Incorrect execution of these components may lead to unsafe or incomplete checkpoint executions.
 
 \begin{figure}
@@ -226,10 +229,11 @@ At the same time, they are likely to operate at sub-normal voltages, as checkpoi
     \label{fig:adc_and_fram_error}
 \end{figure}
 
-Fig.~\ref{fig:adc_error} shows the behavior of ADCs in sub-normal voltage.
+Fig.~\ref{fig:adc_error} shows the behavior of ADCs in sub-normal voltages.
 ADC quantizes the input analog voltage into discrete $2^n$ values, ranging from 0 to the given reference voltage, where $n$ is a resolution.
-Since $n$ is fixed, using smaller reference voltage increases sensitivity of the ADC at the cost of reduced representation range.
-As STM32L5 is designed to use $V_{dd}$ as a reference voltage, accessing the ADC during sub-normal voltage operation leads to inconsistent results.
+Therefore, using smaller reference voltage increases sensitivity of the ADC at the cost of reduced representation range.
+% Since $n$ is fixed, using smaller reference voltage increases sensitivity of the ADC at the cost of reduced representation range.
+As STM32L5 uses $V_{dd}$ as a reference voltage, accessing the ADC during sub-normal voltage operations leads to inconsistent results.
 As shown in the figure, the ADC returns values higher than the measurements since its representation range is decreased as $V_{dd}$ drops.
 As a result, during sub-normal voltage operation, the system may incorrectly interpret ADC results as if there is sufficient energy in $C_{ES}$ and decide not to execute a checkpoint, resulting in loss of the progress during the entire power cycle.