Update on local

sections/OurApproach.tex

@@ -10,9 +10,27 @@
     % \label{fig:hardware_setup}
 \end{figure}
 
-\subsection{Use Vdd for Checkpoint Trigger}
+\subsection{Use Vdd and Known Voltage for Checkpoint Execution}
 \label{sec:use_vdd}
 
+Sec.~\ref{sec:predicting_power_failures} demonstrates that capacitor voltage is not a good estimate for the system's remaining execution time.
+Instead, we propose using Vdd for accurate estimation for imminent power-off, as in works not having power management systems (Sec.~\ref{sec:related_work}).
+Also, utilize a voltage reference with a known value.
+Note that the reference voltage should be lower than the minimal operating voltage of MCU.
+We propose two efficient implementations, each for dynamic and static checkpoint schemes.
+
+T1 utilizes a on-chip comparator (available both in STM32L5 and MSP430).
+Using a voltage divider with two resistors, Vdd is reduced so that the comparator is triggered when the target power-off voltage is reached.
+
+T2 is setup for static checkpoint techniques, which poll the capacitor voltage to determine whether execute checkpoint or not.
+Instead of reading the capacitor voltage, it reads the reference voltage.
+As we discussed in Sec.~\ref{sec:sub_normal_execution}, the voltage remains same while the system executes at normal voltage but the value increases during sub-normal voltage execution.
+
+% \begin{itemize}
+%     \item T1 utilizes a on-chip comparator (available both in STM32L5 and MSP430) with a reference voltage.
+%     \item T2.
+% \end{itemize}
+
 \begin{figure}
     \centering
     \begin{subfigure}{\linewidth}

sections/OurModel.tex

@@ -260,8 +260,8 @@ For both systems, we set architectural parameters to make operation time around
 Fig.~\ref{fig:other_architectures} shows the results in different power-off voltage.
 The bar in the left side shows the energy breakdown in one power cycle, and the one in the right side represents the ratio of the execution time operated at sub-voltage.
 The most noticeable difference is ratio of energy consumed for ramp-up and init.
-While A1 consumes xx\% power at this stage on average, A2 consumes only xx\%.
+While A1 consumes 63.4\% power at this stage on average, A2 consumes only 5.6\%.
 This is because A1 shows larger leakage current due to external MRAM, which consumes more current than FRAM in our case.
-However, both architectures show high sub-voltage execution rates, up to xx\% in A2.
-In addition, discharged energy takes considerable portion both in A1 (xx\%) A2 (xx\%) at 3.3V configuration, which represents the techniques based on the traditional model.
+However, both architectures show high sub-voltage execution rates, up to 70.1\% in A2.
+In addition, discharged energy takes considerable portion both in A1 (31.4\%) and A2 (52.0\%) at 3.3V configuration, which represents the techniques based on the traditional model.
 In summary, the evaluation reveals that the buffering effect of system's capacitance and its implications are general in other systems.

sections/RelatedWork.tex

@@ -1,4 +1,5 @@
 \section{Related Work}
+\label{sec:related_work}
 
 Techniques to find the best hardware configurations (model approaches~\cite{kimRapid2024,houTale2024,erataETAP2023,ghasemiPES2023,sanmiguelEH2018a,sanmiguelEH2018}).
 Tradeoff of capacitor size and forward progress~\cite{zhanExploring2022}.