Update on local

sections/Introduction.tex

@@ -2,7 +2,7 @@
 Batteryless systems are increasingly recognized as a promising future platform of Internet-of-Things (IoT) devices.
 They adopt a small capacitor as an energy storage and operate on power collected from environmental sources.
 This setup efficiently avoids the challenges associated with battery such as human management for recharging/replacing and harmful environmental impacts.
-These systems are also known as intermittent systems, since the computation happens intermittently when there exist sufficient power to compute.
+These systems are also known as intermittent systems, since the computation happens intermittently only when there exist sufficient power to compute.
 
 \begin{figure}
     \centering
@@ -11,28 +11,15 @@ These systems are also known as intermittent systems, since the computation happ
     \label{fig:introduction}
 \end{figure}
 
-Intermittent systems require software support to maintain volatile system states across power failures.
-The volatile system states (e.g., register and memory) should be saved to Non-Volatile Memory (NVM) during the execution and be recovered upon power restoration.
-When designing such technique, software designers rely on an \emph{execution model}, which abstracts the operations in the hardware and describes how intermittent system works.
+An intermittent system requires software support to retain volatile system state information across power interruptions. While the system is running, volatile data, such as that in registers or SRAM, must be saved to non-volatile memory (NVM) and subsequently restored when power resumes, allowing operations to continue. In developing such state-preserving techniques, software designers rely on an execution model that abstracts hardware-level operations and represents the behavior of intermittent systems necessary for software design.
 
-Fig.~\ref{fig:introduction} illustrates this model.
-The voltage of energy storage increases while the system collects energy from environmental sources.
-When the capacitor voltage reaches a certain threshold voltage, the computing system is powered on and starts execution.
-When the capacitor voltage hits a power-off threshold later, the computing system is powered off and energy starts to be collected again.
-The goal of software designers is to implement techniques to sustain system states across power failures with minimal overhead under such execution model.
+Figure 1 illustrates this execution model. As energy is charged, the voltage in the capacitor gradually increases and, upon reaching the power-on threshold, starts supplying power to the system. The system begins operation at this point, and execution is halted when the capacitor reaches the power-off threshold. Software designers aim to leverage this execution model to implement intermittent systems at minimal cost.
 
-Recent techniques have aimed frequent power failures.
-This is typically considered good, better reactiveness.
+This execution model has served as the foundation for many successful intermittent system technologies. However, it may introduce considerable inaccuracies when applied to recent research aimed at very short power supply durations. Short power interruptions generally improve system responsiveness and are therefore considered a desirable trait. Recent studies have explored technologies operating with power supply times in the range of tens of milliseconds or microseconds, often utilizing small capacitors of less than 1mF for energy storage. When capacitors of this scale are used, the system operates in a way that significantly diverges from the traditional model. The primary reason is the presence of a decoupling capacitor on the board—an essential component that maintains system voltage during sudden current changes.
 
-However, this model is not precise enough for recent techniques that aim frequent power failures where power failure frequency is of tens of milliseconds or even in nanosecond scale.
-The major source of inconsistency is the decoupling capacitors in the system.
-Decoupling capacitors are on-board capacitors attached to the power input/output terminal.
-These are mandatory components (Sec.~\ref{sec:system_description}) since they prevent voltage ripples when the system draws huge current suddenly (e.g., for checkpoint execution) by buffering energy.
-They usually have a capacitance ranging from tens (e.g., MSP430) to hundreds (e.g., STM32L5) of uF.
+The decoupling capacitor acts as an energy buffer, creating a deviation from the ideal execution model. 
+When power is supplied to the system, the decoupling capacitor rapidly charges and reduces capacitor voltage. 
+Then the buffered energy continues to power the system even after the power-off threshold is reached. 
+Understanding this effect is crucial for intermittent system designers, as it has a significant impact on both system efficiency and correctness.
 
-They are negligible in battery-powered systems and have small impacts in intermittent systems designed for working more than a second.
-However, to achieve millisecond-level execution time, the system should adopt a tiny capacitor, whose size is comparable to the decoupling capacitors.
-When using the capacitors whose size is comparable to the decoupling capacitors as an energy storage, the real system behaves quite differently than the model presented in Fig.~\ref{fig:introduction}.
-
-In this paper, we propose detailed execution model.
-Understanding this model is critical, especially working with small capacitors, since it significantly affects the power efficiency and even correctness of the intermittent system.
+In this paper, we propose a more accurate execution model for intermittent systems based on the effects of the decoupling capacitor. In Section 2, we demonstrate that checkpoint systems based on the traditional model can be up to six times more energy-inefficient and may fail to predict power-off timings accurately, leading to unsafe checkpointing. Based on this analysis, we propose three design guidelines to implement efficient and safe intermittent systems.

sections/OurModel.tex

@@ -1,34 +1,59 @@
 \section{Detailed Intermittent Execution Model}
 
+In this section, we describe a detailed execution model of intermittent systems based on our observations from the measurement.
+In Sec.~\ref{sec:system_description}, we introduce the typical hardware setup of intermittent systems and the system we collected the data from.
+Sec.~\ref{sec:execution_model} presents the key observations from our measurements and proposes our detailed execution model.
+
 \subsection{System Description}
 \label{sec:system_description}
 
+
 \begin{figure}
     \centering
     \includegraphics[width=\linewidth]{figs/cropped/system.pdf}
     \caption{A typical hardware setup of intermittent systems.}
-    % \label{fig:introduction}
+    \label{fig:hardware_setup}
 \end{figure}
 
+A typical intermittent system consists of two components: a power management system and a computing system.
+Fig.~\ref{fig:hardware_setup} illustrates this setup.
+The power management system is responsible for collecting the incoming power into energy storage and providing a stable-voltage current to the computing system.
+The computing system equips NVMs along with the MCU and peripherals, and utilize the NVMs for state retention between power failures.
+
+This setup has two notable decoupling capacitors that affect the execution model of intermittent systems.
+The first one is attached to the power management system, as voltage regulators need a capacitor larger than the required capacitance for correct execution.
+Also, the computing system also has a decoupling capacitor.
+
+In this work, our goal is to model the buffering effects of these capacitors and evaluate their implications on software designs.
+(Recent studies present the need for better computing capability~\cite{bakarProtean2023a})
+For model validation and evaluation, we use a custom-built board equipped with an ARM Cortex-M33 core and XXMB of FRAM.
+Our setup requires XXuF and 220uF capacitors for C1 and C2, respectively, for stable execution of checkpoint and recovery.
+Sec.~\ref{sec:other_architectures} evaluates our model in different architectures.
+
 \subsection{Execution Model}
+\label{sec:execution_model}
 
 \begin{figure}
     \centering
     \begin{subfigure}{\linewidth}
         \includegraphics[width=\textwidth]{figs/plot_expr_8a_cropped.pdf}
         \caption{Trace of one power cycle.}
-        % \label{fig:eval_voltage_trace}
+        \label{fig:execution_trace_one_cycle}
         \vspace{5pt}
     \end{subfigure}
     \begin{subfigure}{\linewidth}
         \includegraphics[width=\textwidth]{figs/plot_expr_8b_cropped.pdf}
         \caption{Detailed trace.}
-        % \label{fig:eval_adaptivenss_finished_tasks}
+        \label{fig:execution_trace_detailed}
     \end{subfigure}
     \caption{Voltage measurement of capacitor and Vdd (470uF, 1.5mA current supply).}
-    % \label{fig:}
+    \label{fig:execution_trace}
 \end{figure}
 
+Fig.~\ref{fig:execution_trace} shows the voltage trace of the energy storage and the Vdd of the computing system.
+A 470uF capacitor is used for the energy storage to generate execution of xx ms under 1.5mA current supply.
+Fig.~\ref{fig:execution_trace_one_cycle} shows the trace during one power cycle, and Fig.~\ref{fig:execution_trace_detailed} presents the first execution cycle in more detail.
+
 Three key observations that affect software designer's decision.
 
 \begin{itemize}
@@ -44,15 +69,38 @@ Three key observations that affect software designer's decision.
     \label{fig:detailed_execution_model}
 \end{figure}
 
+Fig.~\ref{fig:detailed_execution_model} shows our detailed execution model, which reflects all the key observations.
+
+In the following sections, we discuss how this model benefits the software design.
+
 \subsection{Impact on Power Efficiency}
 
+The traditional model implies that power consumed between power-on and power-off thresholds are entirely used for the computing system (including hardware initialization and recovery).
+However, our model reveals that huge energy is used for charging the decaps (\textbf{O1}) and discharged during power-off durations (\textbf{O3}).
+This implies that much smaller energy is used for the useful computation compared to the designer's expectation.
+
 \begin{figure}
     \centering
     \includegraphics[width=\linewidth]{figs/plot_expr_5_cropped.pdf}
     \caption{Distribution of energy consumed in a power cycle in different capacitor sizes (1mA current supply).}
-    % \label{fig:introduction}
+    \label{fig:power_distribution}
 \end{figure}
 
+Fig.~\ref{fig:power_distribution} shows the distribution of the energy consumed for each stage of intermittent execution within one power cycle, averaged over XX executions, in various capacitor sizes. 
+The line represents the average time of useful computation.
+The checkpoint is executed by the interrupt from the power management system, which is generated when the capacitor voltage reaches the power-off threshold (3.4V).
+Note that this is the last point for checkpoint execution according to the traditional model.
+
+The results shows that significant energy is wasted in decoupling capacitor.
+The cost is more expensive when the capacitor size is small since the decaps discharge rate follows the RC-discharging circuits.
+While using smaller capacitors shortens the power-off durations, the discharging behavior penalizes them most since XX\% of energy is discharged at the first XX ms.
+
+More importantly, this wasted energy is expected to be used for the computation in traditional execution model, as all the energy except for the initialization and checkpoint/recovery is expected to be used in computations.
+It brings significant errors between the two models in available energy for the execution.
+In 470uF case, the actual energy efficiency (Execution) and the expectation from the traditional model (Execution and Discharged) differs by XX times.
+
+(Limitations of power failure injection and simulation based evaluations).
+
 \subsection{Impact on Predicting Power Failures}
 
 \begin{figure}
@@ -72,10 +120,18 @@ Three key observations that affect software designer's decision.
     % \label{fig:}
 \end{figure}
 
-Show percentage of execution time executed after power supply stops.
+According to the traditional model, the system states should be saved to NVM before power-off threshold.
+Our model shows that the system may operate after this point using the energy stored in the decaps (\textbf{O2}). 
+As a result, the energy storage voltage is not a good approximate of the remaining time that system can execute.
 
 \subsection{Impact of Sub-normal Voltage Execution}
 
+The traditional model makes the software designers assume the system is executed under stable voltage.
+However, the execution after the power-off threshold (\textbf{O3}) happens in sub-normal voltage.
+Being aware of this is important to the software designers since the peripherals and analog components may function differently.
+
+The two most critical examples are Analog-Digital Converter (ADC) and external memory.
+
 \begin{figure}
     \centering
     \begin{subfigure}{0.45\linewidth}
@@ -94,27 +150,21 @@ Show percentage of execution time executed after power supply stops.
 \end{figure}
 
 \subsection{Sensitivity to Architectural Designs}
+\label{sec:other_architectures}
 
-% \begin{figure}
-%     \centering
-%     \begin{subfigure}{0.49\linewidth}
-%         \includegraphics[width=\textwidth]{figs/plot_expr_9_cropped.pdf}
-%         \caption{Trace of one power cycle.}
-%         % \label{fig:eval_voltage_trace}
-%     \end{subfigure}
-%     \hfill
-%     \begin{subfigure}{0.49\linewidth}
-%         \includegraphics[width=\textwidth]{figs/plot_expr_9_cropped.pdf}
-%         \caption{Detailed trace.}
-%         % \label{fig:eval_adaptivenss_finished_tasks}
-%     \end{subfigure}
-%     \caption{Voltage of the capacitor and Vdd, sampled 470uF and 1.5mA.}
-%     % \label{fig:}
-% \end{figure}
+Finally, we evaluate our model against two different architectural setups: MSP430 and Cortex-M33 with MRAM.
+MSP430 has less computational capability than Cortex-M33 cores.
+But it is a most popular platform for intermittent system researches, since it is a low-power system having on-chip FRAM.
+We used MSP430FR5994 evaluation board, having 10uF of onboard decap.
+For the second setup, we put MRAM to our evaluation platform instead of FRAM.
+Core frequencies, capacitance of power management system, input power targeting xx ms execution.
 
 \begin{figure}
     \centering
     \includegraphics[width=\linewidth]{figs/plot_expr_9_cropped.pdf}
     \caption{Energy breakdown and the ratio of sub-voltage operations in different architectures.}
-    % \label{fig:detailed_execution_model}
-\end{figure}
+    \label{fig:other_architectures}
+\end{figure}
+
+Fig.~\ref{fig:other_architectures} shows the results in different power-off voltage.
+The bar in the left shows the energy breakdown in one power cycle, and the one in the right represents the ratio of the execution time operated in sub-voltage.