Update on local

sections/OurApproach.tex

@@ -1,9 +1,9 @@
 \section{Design Guidelines}
 \label{sec:design_guidelines}
 
-Based on the insights from our model, we propose design guidelines for efficient and safe intermittent systems.
-The effectiveness of the guidelines is evaluated using seven benchmarks on the reference system used in Sec.~\ref{sec:detailed_execution_model}. 
-We ported five benchmarks from miBench~\cite{guthausMiBench2001} benchmark suite and implemented two computation kernels (\emph{matmul} and \emph{conv2d}) commonly used for evaluating intermittent systems in literature~\cite{kimLACT2024,maengSupporting2019,bhattacharyyaNvMR2022,ganesanWhat2019,akhunovEnabling2023}.
+Based on the insights from our model, we propose design guidelines to implement efficient intermittent systems.
+The effectiveness of these guidelines is evaluated using seven benchmarks on the reference system used in Sec.~\ref{sec:detailed_execution_model}. 
+We ported five benchmarks from miBench~\cite{guthausMiBench2001} benchmark suite and implemented two computation kernels (\emph{matmul} and \emph{conv2d}) commonly used in the evaluation of intermittent systems in the literature~\cite{kimLACT2024,maengSupporting2019,bhattacharyyaNvMR2022,ganesanWhat2019,akhunovEnabling2023}.
 
 We evaluate two popular existing checkpointing schemes: \emph{static} and \emph{dynamic}.
 The static scheme~\cite{ransfordMementos2011,kimLivenessAware2023,kimLACT2024,maengAdaptive2018} inserts checkpoint triggers at every loop latch in the program during compilation.
@@ -30,7 +30,7 @@ On the other hand, our model reveals that significant energy is wasted each time
 \end{figure}
 
 Fig.~\ref{fig:expr_checkpoint_voltages} presents the benchmark execution times in dynamic checkpoint scheme, across various checkpoint execution voltages.
-A 1100 uF capacitor is used as an energy storage and the execution times are normalized to the 3.4V case. 
+A 1100uF capacitor is used as an energy storage and the execution times are normalized to the 3.4V configuration. 
 The results show that executing checkpoints earlier is significantly inefficient: by 1.38x and 2.45x in 3.7V and 4.0V configurations, respectively.
 Moreover, the overhead is consistent across all benchmarks since early checkpoint executions directly reduce the energy available for the computing system.
 Consequently, delaying checkpoint executions is crucial when designing state-retention techniques.
@@ -42,8 +42,9 @@ Achieving this fundamentally depends on accurately predicting imminent power fai
 \label{sec:use_vdd_for_checkpoint}
 
 Sec.~\ref{sec:predicting_power_failures} demonstrates that $V_{ES}$ is not a good estimate for the system's remaining execution time.
-Instead, we propose using $V_{dd}$ to more accurately estimate the imminent power-off events, similar to approaches used in systems without power management system (Sec.~\ref{sec:related_work}).
-Additionally, when obtaining $V_{dd}$, it is important to account for the operations of ADC in sub-normal voltage conditions (Sec.~\ref{sec:sub_normal_execution}).
+Instead, we propose using $V_{dd}$ to more accurately estimate the imminent power-off events, similar to approaches used in works without power management system (Sec.~\ref{sec:related_work}).
+Our setups are designed to work below the normal $V_{dd}$ by accounting for the operations of ADC in sub-normal voltage conditions (Sec.~\ref{sec:sub_normal_execution}).
+% Additionally, when obtaining $V_{dd}$, it is important to account for the operations of ADC in sub-normal voltage conditions (Sec.~\ref{sec:sub_normal_execution}).
 
 For consistent operation of ADCs, we adopt a voltage source with a known value of $V_{ref}$.
 In STM32L5 and MSP430, an internal reference voltage source of 1.2V is available; alternatively, an external voltage reference (e.g., TI LVM431~\cite{texasinstrumentsLMV431}) can be used.
@@ -53,8 +54,8 @@ We propose two efficient implementations, $S_{sta}$ and $S_{dyn}$, to accurately
 $S_{sta}$ is designed for static checkpoint techniques.
 Instead of reading $V_{ES}$ at checkpoint triggers, $S_{sta}$ reads $V_{ref}$. 
 This results in the same value of $\lfloor V_{ref}/V_{dd} \cdot 2^n \rfloor$ when operating on normal voltage, where $n$ is the ADC resolution.
-During sub-voltage execution, this value increases as $V_{dd}$ decreases, as discussed in Sec.~\ref{sec:sub_normal_execution}.
-Given that the target threshold voltage for checkpoint execution is $V_{th}$, software designers can compare the ADC value against $\lfloor V_{ref}/V_{th} \cdot 2^n \rfloor$ to determine whether to execute a checkpoint.
+During sub-normal voltage executions, this value increases as $V_{dd}$ decreases, as discussed in Sec.~\ref{sec:sub_normal_execution}.
+As a result, given that the target threshold voltage for checkpoint execution is $V_{th}$, software designers can compare the ADC value against $\lfloor V_{ref}/V_{th} \cdot 2^n \rfloor$ to determine whether to execute a checkpoint.
 
 On the other hand, $S_{dyn}$ utilizes an on-chip comparator, which is available in most modern MCUs including STM32L5 and MSP430.
 As $V_{ref}$ is always lower than $V_{dd}$, we use a voltage divider consisting of two resistors, $R1$ and $R2$, to scale $V_{dd}$ and compare it with $V_{ref}$.
@@ -94,16 +95,16 @@ Furthermore, these improvements are consistent across all benchmarks, regardless
 
 Another advantage of the proposed setups is their simplicity and practical applicability.
 Since the both setups only modify the method to detect imminent power failures and leave the checkpoint algorithms unchanged, it is straightforward to apply them in existing techniques.
-Furthermore, the proposed setups can reduce the system complexity, as they eliminate the need for communication (e.g., interrupt or access to $V_{ES}$) between the energy storage system and the computing system.
+Furthermore, the proposed setups can reduce the system complexity, as they eliminate the need for communication between the energy storage system and the computing system (e.g., interrupt or access to $V_{ES}$).
 
 % \subsection{Checkpoint Techniques and Evaluation Methods}
 \subsection{On Selecting Hardware Components}
 
-Our model helps designers in selecting efficient hardware components across various parameters.
-For example, it implies that operating voltage of peripherals (e.g., external NVMs) is a critical design consideration (Sec.~\ref{sec:sub_normal_execution}), often more important than other factors such as latency.
+Our model also helps designers in selecting efficient hardware components across various parameters.
+For example, it reveals that operating voltage of peripherals (e.g., external NVMs) is a critical design consideration (Sec.~\ref{sec:sub_normal_execution}), often more important than other factors such as latency.
 % We evaluate this tradeoff by simulating an external FRAM having faster access latency but smaller operating voltage.
 To evaluate this tradeoff, we simulate two FRAM configurations, F1 and F2, in our reference system.
-F1 represents slower setup capable of operating down to 2.5V, achieved by doubling the software-configurable wait time for FRAM accesses.
+F1 represents a slower setup capable of operating down to 2.5V, achieved by doubling the software-configurable wait time for FRAM accesses.
 F2 is set to have the lowest access latency but the system stops at 2.8V.
 
 \begin{figure}
@@ -120,7 +121,7 @@ This example clearly shows that operating voltage, often overlooked in the tradi
 
 Finally, our model highlights advantages of using smaller decoupling capacitors.
 Larger buffers not only increases the ratio of sub-normal voltage operations but also raises the amount of discharged energy during power-offs.
-Indeed, in our reference system with $C_{ES}$ = 1100uF, we observe that it takes xx\% and xx\% longer to complete the benchmarks, when 440uF and 660uF capacitors are used as C2, respectively, compared to our setup with a 220uF capacitor.
+Indeed, in our reference system with $C_{ES}$ = 1100uF, we observe that it takes 1.18x and 1.36x longer to complete the benchmarks, when 440uF and 660uF capacitors are used as C2, respectively, compared to our setup with a 220uF capacitor.
 % As a result, it is a good design practice to use the smallest decoupling capacitors for efficiency of intermittent systems.
 
 % \begin{figure}

sections/OurModel.tex

@@ -207,8 +207,12 @@ The traditional model leads the software designers to assume that the system is
 However, a significant portion of execution may happen after the power-off threshold at sub-normal voltages (\textbf{O3}), as discussed in Sec.~\ref{sec:predicting_power_failures}.
 Being aware of this is crucial to software designers since analog components and peripherals may function differently at sub-normal voltages.
 
-Two of the most relevant examples are Analog-Digital Converters (ADCs) and external NVMs.
-They play an important role in checkpointing: ADCs are commonly used to determine when to execute a checkpoint by reading $V_{ES}$ and NVM serves as the storage for the checkpoints.
+Two relevant examples are Analog-Digital Converters (ADCs) and external NVMs.
+ADCs are commonly used to determine when to execute a checkpoint by reading $V_{ES}$.
+It quantizes the input analog voltage into discrete $2^n$ values, ranging from 0 to the given reference voltage, where $n$ is a resolution.
+Using smaller reference voltage increases sensitivity of ADC at the cost of reduced representation range.
+% They play an important role in checkpointing, since ADCs are commonly used to determine when to execute a checkpoint by reading $V_{ES}$, and NVM serves as the storage for the checkpoints.
+% They play an important role in checkpointing: ADCs are commonly used to determine when to execute a checkpoint by reading $V_{ES}$ and NVM serves as the storage for the checkpoints.
 % At the same time, they are likely to operate at sub-normal voltages, as checkpoint executions typically happen just before the power-off.
 % Incorrect execution of these components may lead to unsafe or incomplete checkpoint executions.
 
@@ -230,12 +234,15 @@ They play an important role in checkpointing: ADCs are commonly used to determin
 \end{figure}
 
 Fig.~\ref{fig:adc_error} shows the behavior of ADCs in sub-normal voltages.
-ADC quantizes the input analog voltage into discrete $2^n$ values, ranging from 0 to the given reference voltage, where $n$ is a resolution.
-Therefore, using smaller reference voltage increases sensitivity of the ADC at the cost of reduced representation range.
+% ADC quantizes the input analog voltage into discrete $2^n$ values, ranging from 0 to the given reference voltage, where $n$ is a resolution.
+% Therefore, using smaller reference voltage increases sensitivity of ADC at the cost of reduced representation range.
 % Since $n$ is fixed, using smaller reference voltage increases sensitivity of the ADC at the cost of reduced representation range.
-As STM32L5 uses $V_{dd}$ as a reference voltage, accessing the ADC during sub-normal voltage operations leads to inconsistent results.
-As shown in the figure, the ADC returns values higher than the measurements since its representation range is decreased as $V_{dd}$ drops.
-As a result, during sub-normal voltage operation, the system may incorrectly interpret ADC results as if there is sufficient energy in $C_{ES}$ and decide not to execute a checkpoint, resulting in loss of the progress during the entire power cycle.
+Because STM32L5 uses $V_{dd}$ as a reference voltage, accessing the ADC under sub-normal voltages produces inconsistent results.
+As shown in the figure, the ADC returns values higher than the actual measurements since its representation range decreases as $V_{dd}$ drops.
+Consequently, ADC may mislead the system into overestimating the energy in $C_{ES}$ during sub-normal voltage executions, potentially leading to checkpoint miss and a loss of progress for the entire power cycle.
+% This can result in failing to execute a checkpoint, leading to the loss of progress during the entire power cycle.
+% As a result, during sub-normal voltage operation, the system may misinterpret ADC results as indicating sufficient energy in $C_{ES}$ and fail to execute a checkpoint, resulting in loss of progress during the power cycle.
+% As a result, during sub-normal voltage operation, the system may inccor ADC results as indicating sufficient energy in $C_{ES}$ and decide not to execute a checkpoint, resulting in loss of the progress during the power cycle.
 
 Also, intermittent systems typically designed to operate with peripherals such as sensors~\cite{yildizAdaptable2024,dangIoTree2022,afanasovBatteryless2020,maengAdaptive2020}, wireless communication modules~\cite{katanbafMultiScatter2021,dewinkelIntermittentlypowered2022,babatundeGreentooth2024} or external NVMs~\cite{dewinkelIntermittentlypowered2022,kimLACT2024,kimLivenessAware2023,akhunovEnabling2023}, which have their own minimum operating voltage requirements.
 % Also, some peripherals may not work below certain voltage.

sections/RelatedWork.tex

@@ -10,6 +10,6 @@ Furthermore, our work proposes several practical guidelines to improve the effic
 In some works that do not have a dedicated power management system and directly supply unregulated power to the computing system~\cite{balsamoHibernus2015,balsamoHibernus2016,netoDiCA2023,raffeckCO2CoDe2024,reymondEarlyBird2024}, $V_{dd}$ has been used as a checkpoint signal.
 This is natural in these works since the voltage of the energy storage is always identical to $V_{dd}$.
 % This is natural in these works since the voltage of the energy storage is always same as Vdd and the MCU operates in varying voltage levels.
-In contrast, our work demonstrates that accounting for sub-normal voltage operation is also critical in systems with regulated power supplies, which represent the majority of intermittent system setups.
+In contrast, our work demonstrates that accounting for sub-normal voltage operations is also critical in systems with regulated power supplies, which represent the majority of intermittent system setups.
 % Especially, this work reveals that these impacts come from the buffering effects of the inherent capacitance, which are not exist in these works.
-Also, we address the impacts of sub-normal voltage execution on the correctness and efficiency of software designs, along with suggestions to exploit such impacts for improved system performance.
+Also, we address the impacts of sub-normal voltage executions on the correctness and efficiency of software designs, along with suggestions to exploit such impacts for improved system performance.