Update on local

IEEE-conference-template-062824.tex

@@ -27,14 +27,14 @@
 
 \title{Intermittent Systems at Small Scale: Execution Model and Design Guidelines \\
 % \thanks{This work was supported by IITP grant funded by the Korea government (MSIT) (No.2021-0-00360, Development of Core Technology for Autonomous Energy-driven Computing System SW in Power-instable Environment).}
-% \thanks{This work was supported by IITP grant funded by the Korea government (MSIT) (No.2021-0-00360).}
+\thanks{This work was supported by IITP grant funded by the Korea government (MSIT) (No.2021-0-00360).}
 }
 
-% \author{\IEEEauthorblockN{Youngbin Kim and Yoojin Lim}
-% \IEEEauthorblockA{yb.kim@etri.re.kr, yoojin.lim@etri.re.kr \\
-% Electronics and Telecommunications Research Institute (ETRI), Daejeon, Republic of Korea
-% }
-% }
+\author{\IEEEauthorblockN{Youngbin Kim and Yoojin Lim}
+\IEEEauthorblockA{yb.kim@etri.re.kr, yoojin.lim@etri.re.kr \\
+Electronics and Telecommunications Research Institute (ETRI), Daejeon, Republic of Korea
+}
+}
 
 \maketitle
 

refs_short_2.bib

@@ -2,7 +2,6 @@
   author =        {Choi, Jongouk and others},
   series =        {RTAS '22},
   month =         may,
-  pages =         {40--54},
   title =         {Compiler-{{Directed High-Performance Intermittent
                    Computation}} with {{Power Failure Immunity}}},
   year =          {2022},
@@ -52,7 +51,6 @@
   author =        {Maeng, Kiwan and Lucia, Brandon},
                    series = {PLDI '20'},
   month =         jun,
-  pages =         {1005--1021},
   publisher =     {ACM},
   title =         {Adaptive Low-Overhead Scheduling for Periodic and
                    Reactive Intermittent Execution},
@@ -77,7 +75,6 @@
   author =        {Hou, Xiaofeng and others},
   series =        {ISCA '24},
   month =         jun,
-  pages =         {167--181},
   title =         {A {{Tale}} of {{Two Domains}}: {{Exploring Efficient
                    Architecture Design}} for {{Truly Autonomous
                    Things}}},
@@ -114,7 +111,6 @@
   author =        {San Miguel, Joshua and others},
   series =        {MICRO '18},
   month =         oct,
-  pages =         {600--612},
   title =         {The {{EH Model}}: {{Early Design Space Exploration}}
                    of {{Intermittent Processor Architectures}}},
   year =          {2018},
@@ -125,7 +121,6 @@
   author =        {Maeng, Kiwan and Lucia, Brandon},
                    series = {PLDI '19},
   month =         jun,
-  pages =         {1101--1116},
   publisher =     {ACM},
   title =         {Supporting Peripherals in Intermittent Systems with
                    Just-in-Time Checkpoints},

sections/Introduction.tex

@@ -10,7 +10,7 @@ During operation, volatile data (e.g., registers or SRAM data) must be saved to
 When power is restored, this saved state is recovered to allow operations to resume the execution from the last checkpoint (recovery). 
 In designing these state retention techniques, software designers rely on an \emph{execution model} that abstracts hardware-level operations and represents behavior of intermittent systems necessary for software design.
 
-Fig.~\ref{fig:introduction} illustrates such execution model commonly adopted in literature~\cite{ransfordMementos2011,jayakumarQUICKRECALL2014,maengAdaptive2020,dewinkelIntermittentlypowered2022,houTale2024,erataETAP2023,ghasemiPES2023,sanmiguelEH2018a}. 
+Fig.~\ref{fig:introduction} illustrates such execution model commonly adopted in the literature~\cite{ransfordMementos2011,jayakumarQUICKRECALL2014,maengAdaptive2020,dewinkelIntermittentlypowered2022,houTale2024,erataETAP2023,ghasemiPES2023,sanmiguelEH2018a}. 
 As energy accumulates, the voltage of the capacitor gradually increases.
 Once the voltage reaches the power-on threshold $V_h$, the collected power is supplied to the system. 
 The system begins operation at this point, and execution is halted when the capacitor voltage reaches the power-off threshold $V_l$. 

sections/OurApproach.tex

@@ -6,11 +6,11 @@ The effectiveness of these guidelines is evaluated using seven benchmarks on the
 We ported five benchmarks from miBench~\cite{guthausMiBench2001} benchmark suite and implemented two computation kernels (\emph{matmul} and \emph{conv2d}) commonly used in the evaluation of intermittent systems in the literature~\cite{kimLACT2024,maengSupporting2019,bhattacharyyaNvMR2022,ganesanWhat2019,akhunovEnabling2023}.
 
 We evaluate two popular existing checkpointing schemes: \emph{static} and \emph{dynamic}.
-In \emph{static}, checkpoint triggers are inserted at every loop latch in the program during compilation~\cite{ransfordMementos2011,kimLivenessAware2023,kimLACT2024,maengAdaptive2018}.
+In \emph{static}, checkpoint triggers are inserted at the back-edge of every loop in the program during compilation~\cite{ransfordMementos2011,kimLivenessAware2023,kimLACT2024,maengAdaptive2018}.
 At runtime, checkpoint triggers examine $V_{ES}$ and execute checkpoint only when it is below a predefined threshold.
 In contrast, \emph{dynamic}~\cite{jayakumarQUICKRECALL2014,maengSupporting2019,balsamoHibernus2016,balsamoHibernus2015,kortbeekTimesensitive2020} does not modify the original program code.
 Instead, it executes checkpoints via interrupts from the power management system, generated when $V_{ES}$ reaches $V_l$.
-These schemes are considered since most checkpoint techniques utilize $V_{ES}$ by either actively polling it (as in \emph{static}) or by receiving a signal (as in \emph{dynamic}).
+These schemes are considered since most checkpoint techniques utilize $V_{ES}$ either by actively polling it (as in \emph{static}) or by receiving external signals generated based on $V_{ES}$ levels (as in \emph{dynamic}).
 All the evaluations are conducted with 470uF energy storage and 1mA of input current at 1.9V, unless otherwise stated.
 
 \subsection{Delaying Checkpoint Executions}
@@ -134,8 +134,8 @@ F2 is set to have the lowest access latency but requires the system stop operati
 
 Fig.~\ref{fig:expr_peripheral_voltage} presents the execution times of the benchmarks for the two configurations in $S_{dyn}$, averaged over 30 runs.
 Despite its doubled latency, F1 completes the workloads 1.46x faster on average, with consistent improvements across all benchmarks.
-These results suggest that using slower FRAM that operates until 1.8V (e.g.,~\cite{fujitsuMB85R4M2T}) could considerably improve the performance of our reference system.
-This example clearly shows that operating voltage, often overlooked in the traditional model, should be considered a critical design parameter.
+These results imply that using slower FRAM that operates until 1.8V (e.g.,~\cite{fujitsuMB85R4M2T}) could considerably improve the performance of our reference system.
+This example highlights that operating voltage, often overlooked in the traditional model, should be considered a critical design parameter.
 
 Finally, our model highlights advantages of using smaller decoupling capacitors.
 Larger buffers not only increases the ratio of sub-normal voltage operations but also raise the amount of discharged energy during power-offs.

sections/OurModel.tex

@@ -4,7 +4,7 @@
 In this section, we describe our execution model and its implications for software design.
 Sec.~\ref{sec:system_description} introduces the target architecture and the reference system used for evaluations.
 Sec.~\ref{sec:execution_model} presents our execution model, derived from key observations obtained through experimental results.
-In the subsequent three sections, we discuss how this model affects both the power efficiency and correctness of software design.
+In the following three sections, we discuss how this model affects both the power efficiency and correctness of software design.
 Finally, in Sec.~\ref{sec:other_architectures}, we evaluate the effectiveness of our model across systems with various architectural configurations. 
 
 \subsection{Target Architecture and Reference System}
@@ -203,11 +203,11 @@ In Sec.~\ref{sec:use_vdd_for_checkpoint}, we validate this aspect and propose me
 \subsection{Impact of Sub-normal Voltage Execution}
 \label{sec:sub_normal_execution}
 
-The traditional model leads the software designers to assume that the system is executed under a stable voltage.
+The traditional model leads software designers to assume that the system is executed under a stable voltage.
 However, a significant portion of execution may happen after the power-off threshold at sub-normal voltages (\textbf{O3}), as discussed in Sec.~\ref{sec:predicting_power_failures}.
 Being aware of this is crucial to software designers since analog components and peripherals may function differently at sub-normal voltages.
-
 Two relevant examples are Analog-Digital Converters (ADCs) and external NVMs.
+
 ADCs are commonly used to determine when to execute a checkpoint by reading $V_{ES}$.
 It quantizes the input analog voltage into discrete $2^n$ values, ranging from 0 to the given reference voltage, where $n$ is a resolution.
 Using smaller reference voltage increases sensitivity of ADC at the cost of reduced representation range.
@@ -233,7 +233,7 @@ Using smaller reference voltage increases sensitivity of ADC at the cost of redu
     \label{fig:adc_and_fram_error}
 \end{figure}
 
-Fig.~\ref{fig:adc_error} shows the behavior of ADCs in sub-normal voltages.
+Fig.~\ref{fig:adc_error} shows the behavior of ADCs, where the execution in sub-normal voltages are depicted in gray.
 % ADC quantizes the input analog voltage into discrete $2^n$ values, ranging from 0 to the given reference voltage, where $n$ is a resolution.
 % Therefore, using smaller reference voltage increases sensitivity of ADC at the cost of reduced representation range.
 % Since $n$ is fixed, using smaller reference voltage increases sensitivity of the ADC at the cost of reduced representation range.
@@ -280,7 +280,7 @@ Table~\ref{tab:architectures} shows the detailed parameters of the target archit
 A1 shares the same configuration as the reference system but equips MRAM (Everspin MR5A16ACYS35), which is gaining attention as a next generation NVM~\cite{akhunovEnabling2023,bakarProtean2023a,dewinkelIntermittentlypowered2022,wuIntOS2024}, instead of FRAM.
 % This setup is included since MRAM is also gaining attention as a next generation NVM~\cite{akhunovEnabling2023,bakarProtean2023a,dewinkelIntermittentlypowered2022,wuIntOS2024}.
 Second target is MSP430 equipped with on-chip FRAM, a widely adopted 16-bit platform in intermittent system research.
-For both systems, the architectural parameters are set to achieve an operation time of approximately 50 ms.
+For both systems, the architectural parameters are configured to achieve an operation time of approximately 50 ms.
 
 \begin{figure}
     \centering