Update on local

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@@ -9,4 +9,5 @@ IEEE-conference-template-062824.pdf
 *.synctex*
 *.bbl
 *.blg
-~$*.*
+~$*.*
+.vscode

IEEE-conference-template-062824.tex

@@ -15,14 +15,13 @@
 
 % \title{Intermittent Systems with Small Scale: Model and Design Guidelines \\
 \title{Intermittent Systems in Small Scale: Execution Model and Design Guidelines \\
-% \thanks{Identify applicable funding agency here. If none, delete this.}
+\thanks{This work was supported by IITP grant funded by the Korea government (MSIT) (No.2021-0-00360, Development of Core Technology for Autonomous Energy-driven Computing System SW in Power-instable Environment).}
 }
 
-\author{\IEEEauthorblockN{1\textsuperscript{st} Given Name Surname}
-\IEEEauthorblockA{\textit{dept. name of organization (of Aff.)} \\
-\textit{name of organization (of Aff.)}\\
-City, Country \\
-email address or ORCID}
+\author{\IEEEauthorblockN{Youngbin Kim and Yoojin Lim}
+\IEEEauthorblockA{yb.kim@etri.re.kr, yoojin.lim@etri.re.kr \\
+Electronics and Telecommunications Research Institute (ETRI), Daejeon, Republic of Korea
+}
 }
 
 \maketitle

sections/Introduction.tex

@@ -1,25 +1,60 @@
 \section{Introduction}
-Batteryless systems are increasingly recognized as a promising future platform of Internet-of-Things (IoT) devices.
-They adopt a small capacitor as an energy storage and operate on power collected from environmental sources.
-This setup efficiently avoids the challenges associated with battery such as human management for recharging/replacing and harmful environmental impacts.
+Batteryless systems are emerging as a promising future platform of Internet-of-Things (IoT) devices.
+These systems adopt a small capacitor as an energy storage and operate by harvesting power from environmental sources.
+This setup effectively addresses challenges associated with traditional battery-based systems, such as need for human intervention for recharging or replacement~\cite{choiCompilerDirected2022} and harmful environmental impacts~\cite{ahmedInternet2024}.
 These systems are also known as intermittent systems, since the computation happens intermittently only when there exist sufficient power to compute.
 
-\begin{figure}
+Intermittent systems require software support to sustain long-running executions across power failures.
+% An intermittent system requires software support to retain volatile system state information across power interruptions. 
+During operation, volatile data (e.g., registers or SRAM data) must be saved to Non-Volatile Memories (NVMs) through a process known as checkpointing.
+When power is restored, this saved state is restored to allow operations to resume from the context before the power failure (recovery). 
+In designing these state retention techniques, software designers rely on an \emph{execution model} that abstracts hardware-level operations and represents behavior of intermittent systems necessary for software design.
+
+Figure 1 illustrates this execution model. 
+As energy accumulates, the voltage of the capacitor gradually increases.
+And upon reaching the power-on threshold, the collected power is supplied to the system. 
+The system begins operation at this point, and execution is halted when the capacitor reaches the power-off threshold. 
+Software designers aim to leverage this execution model to implement intermittent systems at minimal cost.
+
+\begin{figure}[t]
     \centering
     \includegraphics[width=\linewidth]{figs/cropped/intermittent_computing.pdf}
     \caption{Traditional execution model of intermittent systems.}
     \label{fig:introduction}
 \end{figure}
 
-An intermittent system requires software support to retain volatile system state information across power interruptions. While the system is running, volatile data, such as that in registers or SRAM, must be saved to non-volatile memory (NVM) and subsequently restored when power resumes, allowing operations to continue. In developing such state-preserving techniques, software designers rely on an execution model that abstracts hardware-level operations and represents the behavior of intermittent systems necessary for software design.
 
-Figure 1 illustrates this execution model. As energy is charged, the voltage in the capacitor gradually increases and, upon reaching the power-on threshold, starts supplying power to the system. The system begins operation at this point, and execution is halted when the capacitor reaches the power-off threshold. Software designers aim to leverage this execution model to implement intermittent systems at minimal cost.
+In the meantime, researches on intermittent systems are increasingly exploring shorter operation time by using smaller capacitors.
+Operate on small capacitors is generally desirable, as it not only reduces device volume but also enhances the responsiveness by enabling the system to wake up more frequently~\cite{bakarProtean2023a,maengAdaptive2020,alsubhiStash2024}.
+As a result, recent studies have targeted operation times in the range of tens of milliseconds~\cite{reymondSCHEMATIC2024,wuIntOS2024,yildizEfficient2023,choiCompilerDirected2022} or even microseconds~\cite{reymondSCHEMATIC2024,wuIntOS2024}.
+However, as energy storage size decreases, the traditional execution model no longer provides an accurate abstraction of actual execution behavior.
+% The challenge is that the traditional execution model does not provide precise abstraction of the real execution anymore when the energy storage is very small.
+The major source of this discrepancy is the buffering effect of decoupling capacitors, which is overlooked in the traditional model, as their size was considered negligible compared to the main energy storage.
+
+Decoupling capacitors are on-board capacitors that act as energy buffers.
+They are mandatory components since the buffered energy prevent transient voltage drop when the system suddenly draws a large current such as during checkpointing (Sec.~\ref{sec:system_description}).
+However, their buffering effect introduces discrepancies between the execution model and the actual system behavior.
+For example, when the system powers on, decoupling capacitors are quickly charged using the energy in the storage, making the energy storage voltage an unreliable estimate of available energy.
+This buffered energy also allows the system operate for a while at a sub-normal voltage after the power supply is stopped.
+Additionally, between power cycles, decoupling capacitors discharge due to the resistance of the system, which significantly lowers the power efficiency.
+In systems with small capacitors, these effects dominate the behaviors modeled in the traditional model.
+Consequently, techniques that are highly efficient according to the traditional model may introduce substantial power overhead and even correctness issues in small-scale systems.
+% Consequently, designing software techniques based on the traditional model brings significant power overhead and even correctness issues, even they are extremely efficient in the traditional model.
+% While this seems merely delaying the start and the end of the operations at first glance, we will show that it significantly affects the power efficiency and even correctness of software designs.
 
-This execution model has served as the foundation for many successful intermittent system technologies. However, it may introduce considerable inaccuracies when applied to recent research aimed at very short power supply durations. Short power interruptions generally improve system responsiveness and are therefore considered a desirable trait. Recent studies have explored technologies operating with power supply times in the range of tens of milliseconds or microseconds, often utilizing small capacitors of less than 1mF for energy storage. When capacitors of this scale are used, the system operates in a way that significantly diverges from the traditional model. The primary reason is the presence of a decoupling capacitor on the board—an essential component that maintains system voltage during sudden current changes.
+% This execution model has served as the foundation for many successful intermittent system technologies. 
+% However, it may introduce considerable inaccuracies when applied to recent research aimed at very short power supply durations. 
+% Short power interruptions generally improve system responsiveness and are therefore considered a desirable trait. 
+% Recent studies have explored technologies operating with power supply times in the range of tens of milliseconds or microseconds, often utilizing small capacitors of less than 1mF for energy storage. 
+% When capacitors of this scale are used, the system operates in a way that significantly diverges from the traditional model. 
+% The primary reason is the presence of a decoupling capacitor on the board—an essential component that maintains system voltage during sudden current changes.
 
-The decoupling capacitor acts as an energy buffer, creating a deviation from the ideal execution model. 
-When power is supplied to the system, the decoupling capacitor rapidly charges and reduces capacitor voltage. 
-Then the buffered energy continues to power the system even after the power-off threshold is reached. 
-Understanding this effect is crucial for intermittent system designers, as it has a significant impact on both system efficiency and correctness.
+% The decoupling capacitor acts as an energy buffer, creating a deviation from the ideal execution model. 
+% When power is supplied to the system, the decoupling capacitor rapidly charges and reduces capacitor voltage. 
+% Then the buffered energy continues to power the system even after the power-off threshold is reached. 
+% Understanding this effect is crucial for intermittent system designers, as it has a significant impact on both system efficiency and correctness.
 
-In this paper, we propose a more accurate execution model for intermittent systems based on the effects of the decoupling capacitor. In Section 2, we demonstrate that checkpoint systems based on the traditional model can be up to six times more energy-inefficient and may fail to predict power-off timings accurately, leading to unsafe checkpointing. Based on this analysis, we propose three design guidelines to implement efficient and safe intermittent systems.
+In this paper, we propose a detailed execution model for intermittent systems including the effects of decoupling capacitors. 
+In Section 2, we demonstrate that understanding this model is critical for software designers. 
+Our evaluation shows that intermittent systems designed upon the traditional model can be up to six times more energy-inefficient and may fail to predict power-off timings accurately, leading to unsafe checkpointing. 
+Based on the insights from the detailed model, we propose design guidelines to implement efficient and safe intermittent systems.

sections/OurApproach.tex

@@ -11,4 +11,11 @@
     % \label{fig:detailed_execution_model}
 \end{figure}
 
+\begin{figure}
+    \centering
+    \includegraphics[width=\linewidth]{figs/plot_expr_11_cropped.pdf}
+    \caption{Caption (static).}
+    % \label{fig:detailed_execution_model}
+\end{figure}
+
 \subsection{Design Checkpoint Techniques for Sufficient Power Duration}

sections/OurModel.tex

@@ -1,13 +1,14 @@
 \section{Detailed Intermittent Execution Model}
 
-In this section, we describe a detailed execution model of intermittent systems based on our observations from the measurement.
-In Sec.~\ref{sec:system_description}, we introduce the typical hardware setup of intermittent systems and the system we collected the data from.
-Sec.~\ref{sec:execution_model} presents the key observations from our measurements and proposes our detailed execution model.
+In this Section, we provide a detailed description of our execution model for intermittent systems and its implications for software design.
+In Sec.~\ref{sec:system_description}, we introduce the target hardware setup of our model and the reference system used for evaluations.
+Sec.~\ref{sec:execution_model} presents our proposed execution model, designed based on the key observations from our measurements.
+In the following three sections, we discuss how this model affects both the power efficiency and correctness of software design.
+Finally, in Sec.~\ref{sec:other_architectures}, we evaluate the effectiveness of our model across systems with different architectural configurations. 
 
 \subsection{System Description}
 \label{sec:system_description}
 
-
 \begin{figure}
     \centering
     \includegraphics[width=\linewidth]{figs/cropped/system.pdf}
@@ -15,20 +16,26 @@ Sec.~\ref{sec:execution_model} presents the key observations from our measuremen
     \label{fig:hardware_setup}
 \end{figure}
 
-A typical intermittent system consists of two components: a power management system and a computing system.
-Fig.~\ref{fig:hardware_setup} illustrates this setup.
-The power management system is responsible for collecting the incoming power into energy storage and providing a stable-voltage current to the computing system.
+A typical intermittent system consists of two main components: a power management system and a computing system, as illustrated in Fig.~\ref{fig:hardware_setup}.
+The power management system is responsible for accumulating the incoming energy into storage and providing a stable-voltage current to the computing system.
 The computing system equips NVMs along with the MCU and peripherals, and utilize the NVMs for state retention between power failures.
 
-This setup has two notable decoupling capacitors that affect the execution model of intermittent systems.
-The first one is attached to the power management system, as voltage regulators need a capacitor larger than the required capacitance for correct execution.
-Also, the computing system also has a decoupling capacitor.
+This setup includes two notable decoupling capacitors that affect the execution model of intermittent systems.
+The first one (C1 in the figure) is placed at the power management system as voltage regulators require a capacitor larger than the device-specific minimum capacitance for stable operation.
+Also, the computing system has its own decoupling capacitor (C2) to stabilize operating voltage.
+
+Recent studies increasingly consider use of 32-bit architectures for the computation system~\cite{shihIntermittent2024,wuIntOS2024,kimRapid2024,akhunovEnabling2023,kimLACT2024,kimLivenessAware2023,parkEnergyHarvestingAware2023,kortbeekWARio2022,khanDaCapo2023}, as emerging applications on intermittent systems, such as DNNs, demand more computing capability~\cite{bakarProtean2023a,carontiFinegrained2023}.
+% Emerging intermittent applications demand increasing computing capability~\cite{bakarProtean2023a} due to computat
+To this end, we use a custom-built board equipped with an ARM Cortex-M33 running at 16MHz and 512KB of FRAM as a reference system for validation and evaluation.
+For power management system, we use TI BQ25570 based system.
+We empirically choose XXuF and 220uF capacitors for C1 and C2, respectively, as minimum capacitor sizes for stable execution of checkpoint and recovery.
+Sec.~\ref{sec:other_architectures} evaluates our model in different architectures, such as systems with MRAM and 16-bit core.
 
-In this work, our goal is to model the buffering effects of these capacitors and evaluate their implications on software designs.
-(Recent studies present the need for better computing capability~\cite{bakarProtean2023a})
-For model validation and evaluation, we use a custom-built board equipped with an ARM Cortex-M33 core and XXMB of FRAM.
-Our setup requires XXuF and 220uF capacitors for C1 and C2, respectively, for stable execution of checkpoint and recovery.
-Sec.~\ref{sec:other_architectures} evaluates our model in different architectures.
+% In this work, our goal is to model the buffering effects of these capacitors and evaluate their implications on software designs.
+% (Recent studies present the need for better computing capability~\cite{bakarProtean2023a})
+% For model validation and evaluation, we use a custom-built board equipped with an ARM Cortex-M33 core and 512KB of FRAM.
+% Our setup requires XXuF and 220uF capacitors for C1 and C2, respectively, for stable execution of checkpoint and recovery.
+% Sec.~\ref{sec:other_architectures} evaluates our model in different architectures.
 
 \subsection{Execution Model}
 \label{sec:execution_model}
@@ -51,7 +58,7 @@ Sec.~\ref{sec:other_architectures} evaluates our model in different architecture
 \end{figure}
 
 Fig.~\ref{fig:execution_trace} shows the voltage trace of the energy storage and the Vdd of the computing system.
-A 470uF capacitor is used for the energy storage to generate execution of xx ms under 1.5mA current supply.
+A 470uF capacitor is used for the energy storage to generate execution of about 48 ms under 1.5mA current supply.
 Fig.~\ref{fig:execution_trace_one_cycle} shows the trace during one power cycle, and Fig.~\ref{fig:execution_trace_detailed} presents the first execution cycle in more detail.
 
 Three key observations that affect software designer's decision.
@@ -86,18 +93,19 @@ This implies that much smaller energy is used for the useful computation compare
     \label{fig:power_distribution}
 \end{figure}
 
-Fig.~\ref{fig:power_distribution} shows the distribution of the energy consumed for each stage of intermittent execution within one power cycle, averaged over XX executions, in various capacitor sizes. 
+Fig.~\ref{fig:power_distribution} shows the distribution of the energy consumed for each stage of intermittent execution within one power cycle, averaged over 50 executions, in various capacitor sizes. 
 The line represents the average time of useful computation.
 The checkpoint is executed by the interrupt from the power management system, which is generated when the capacitor voltage reaches the power-off threshold (3.4V).
 Note that this is the last point for checkpoint execution according to the traditional model.
 
 The results shows that significant energy is wasted in decoupling capacitor.
+60.7\% of power is wasted in 470uF, 28.5\% in 1320uF case.
 The cost is more expensive when the capacitor size is small since the decaps discharge rate follows the RC-discharging circuits.
-While using smaller capacitors shortens the power-off durations, the discharging behavior penalizes them most since XX\% of energy is discharged at the first XX ms.
+While using smaller capacitors shortens the power-off durations, the discharging behavior penalizes them most since RC-discharging circuits discharge exponential (in our case, 50\% of energy is discharged at the first 161 ms).
 
 More importantly, this wasted energy is expected to be used for the computation in traditional execution model, as all the energy except for the initialization and checkpoint/recovery is expected to be used in computations.
 It brings significant errors between the two models in available energy for the execution.
-In 470uF case, the actual energy efficiency (Execution) and the expectation from the traditional model (Execution and Discharged) differs by XX times.
+In 470uF case, the actual energy efficiency (Execution) and the expectation from the traditional model (Execution and Discharged) differs by 4.99 times.
 
 (Limitations of power failure injection and simulation based evaluations).
 
@@ -157,7 +165,7 @@ MSP430 has less computational capability than Cortex-M33 cores.
 But it is a most popular platform for intermittent system researches, since it is a low-power system having on-chip FRAM.
 We used MSP430FR5994 evaluation board, having 10uF of onboard decap.
 For the second setup, we put MRAM to our evaluation platform instead of FRAM.
-Core frequencies, capacitance of power management system, input power targeting xx ms execution.
+Core frequencies, capacitance of power management system, input power targeting about 50 ms execution.
 
 \begin{figure}
     \centering

sections/RelatedWork.tex

@@ -5,6 +5,6 @@ Tradeoff of capacitor size and forward progress~\cite{zhanExploring2022}.
 These works do not consider discharge of decoupling capacitor.
 
 Considering sub-normal voltage execution~\cite{zhanExploring2022}.
-In transient computing~\cite{balsamoHibernus2015,balsamoHibernus2016,netoDiCA2023,raffeckCO2CoDe2024} (works do not using separate power management system) or hardware-based approaches.
+In transient computing~\cite{balsamoHibernus2015,balsamoHibernus2016,netoDiCA2023,raffeckCO2CoDe2024,reymondEarlyBird2024} (works do not using separate power management system) or hardware-based approaches.
 This work shows that considering sub-normal voltage execution is also important for designs using separate energy management system.
 They do not address the impact of sub-normal voltage execution to correctness and efficiency of software designs.