Update on local

sections/Introduction.tex

@@ -2,19 +2,19 @@
 Batteryless systems are emerging as a promising future platform of Internet-of-Things (IoT) devices.
 These systems adopt a small capacitor as an energy storage and operate by harvesting power from environmental sources.
 This setup effectively addresses challenges associated with traditional battery-based systems, such as need for human intervention for recharging or replacement~\cite{choiCompilerDirected2022} and harmful environmental impacts~\cite{ahmedInternet2024}.
-They are also known as intermittent systems, since the computation happens intermittently during short time only when there exist sufficient power to compute.
+They are also known as intermittent systems, since the computation happens intermittently during short periods only when there exist sufficient power to compute.
 
 Intermittent systems require software supports to sustain long-running executions across power failures.
 % An intermittent system requires software support to retain volatile system state information across power interruptions. 
-During operation, volatile data (e.g., registers or SRAM data) must be saved to Non-Volatile Memories (NVMs) through a process known as checkpointing.
-When power is restored, this saved state is recovered to allow operations to resume the execution from the last saved context (recovery). 
+During operation, volatile data (e.g., registers or SRAM data) must be saved to Non-Volatile Memory (NVM) through a process called checkpointing.
+When power is restored, this saved state is recovered to allow operations to resume the execution from the last checkpoint (recovery). 
 In designing these state retention techniques, software designers rely on an \emph{execution model} that abstracts hardware-level operations and represents behavior of intermittent systems necessary for software design.
 
-Figure 1 illustrates such execution model commonly adopted in literature~\cite{}. 
+Fig.~\ref{fig:introduction} illustrates such execution model commonly adopted in literature~\cite{ransfordMementos2011,jayakumarQUICKRECALL2014,maengAdaptive2020,dewinkelIntermittentlypowered2022,houTale2024,erataETAP2023,ghasemiPES2023,sanmiguelEH2018a}. 
 As energy accumulates, the voltage of the capacitor gradually increases.
-Upon reaching the power-on threshold, the collected power is supplied to the system. 
+Once the voltage reaches the power-on threshold, the collected power is supplied to the system. 
 The system begins operation at this point, and execution is halted when the capacitor voltage reaches the power-off threshold. 
-Software designers aim to leverage this execution model to implement intermittent systems at minimal cost (e.g., executing checkpoints just before power-off threshold~\cite{}).
+Software designers aim to leverage this execution model to implement intermittent systems at minimal cost (e.g., executing checkpoints just before reaching the power-off threshold~\cite{jayakumarQUICKRECALL2014,maengSupporting2019,maengAdaptive2020,kortbeekBFree2020,netoDiCA2023}).
 
 \begin{figure}[t]
     \centering
@@ -24,22 +24,23 @@ Software designers aim to leverage this execution model to implement intermitten
 \end{figure}
 
 
-In the meantime, researches on intermittent systems are increasingly exploring shorter operation times by using smaller capacitors (e.g., less than 1mF~\cite{ahmedEfficient2019}).
-Operating on small capacitors is generally desirable, as it not only reduces device volume but also enhances the responsiveness by enabling the system to wake up more frequently~\cite{bakarProtean2023a,maengAdaptive2020,alsubhiStash2024}.
+In the meantime, recent research on intermittent systems is increasingly exploring shorter operation times by using smaller capacitors.
+% In the meantime, researches on intermittent systems are increasingly exploring shorter operation times by using smaller capacitors (e.g., less than 1mF~\cite{ahmedEfficient2019}).
+Operating on small capacitors is generally desirable, as it reduces device volume and enhances the responsiveness by enabling the system to wake up more frequently~\cite{bakarProtean2023a,maengAdaptive2020,alsubhiStash2024}.
 As a result, recent studies have targeted operation times in the range of tens of milliseconds~\cite{reymondSCHEMATIC2024,wuIntOS2024,yildizEfficient2023,choiCompilerDirected2022} or even microseconds~\cite{reymondSCHEMATIC2024,wuIntOS2024}.
 % However, as energy storage size decreases, the traditional execution model no longer provides an accurate abstraction of actual execution behavior.
-However, as energy storage size decreases, the traditional execution model is failing to provide an accurate abstraction of actual execution behavior.
+However, as energy storage sizes decrease, the traditional execution model is failing to provide an accurate abstraction of actual execution behavior.
 % The challenge is that the traditional execution model does not provide precise abstraction of the real execution anymore when the energy storage is very small.
 The major source of this discrepancy is the buffering effect of the system's inherent capacitance, mostly coming from its decoupling capacitors.
-This aspect is overlooked in the traditional model, as the inherent capacitance was considered negligible compared to that of the main energy storage.
+This factor has been overlooked in the traditional model, as the inherent capacitance was considered negligible compared to the main energy storage.
 
 Decoupling capacitors are on-board capacitors that act as energy buffers.
 They are mandatory components since the buffered energy prevent transient voltage drop when the system suddenly draws a large current, such as during checkpointing (Sec.~\ref{sec:system_description}).
 However, at the same time, their buffering effect introduces discrepancies between the execution model and the actual system behavior.
-For example, when the system powers on, decoupling capacitors are quickly charged using the energy in the storage, making capacitor voltage an unreliable estimate of available energy.
-This buffered energy also allows the system operate for a while at a sub-normal voltage after the power supply is stopped.
+For example, during powers on, decoupling capacitors are rapidly charged using the energy in the storage, making capacitor voltage an unreliable estimate of available energy.
+This buffered energy also allows the system operate for a while at sub-normal voltages after the power supply is stopped.
 Additionally, between power cycles, decoupling capacitors discharge due to the resistance of the system, considerably lowering the power efficiency.
-In the systems with small capacitors, these effects dominate the behaviors that are modeled in the traditional execution model.
+In systems with smaller capacitors, these effects dominate the behaviors that are modeled in the traditional execution model.
 Consequently, highly efficient techniques according to the traditional model may introduce substantial power overhead and even correctness issues in small-scale systems.
 % Consequently, designing software techniques based on the traditional model brings significant power overhead and even correctness issues, even they are extremely efficient in the traditional model.
 % While this seems merely delaying the start and the end of the operations at first glance, we will show that it significantly affects the power efficiency and even correctness of software designs.
@@ -56,8 +57,8 @@ Consequently, highly efficient techniques according to the traditional model may
 % Then the buffered energy continues to power the system even after the power-off threshold is reached. 
 % Understanding this effect is crucial for intermittent system designers, as it has a significant impact on both system efficiency and correctness.
 
-In this paper, we propose a new execution model for intermittent systems which includes the buffering effects of decoupling capacitors.
+In this paper, we propose a new execution model for intermittent systems which accounts for the buffering effects of decoupling capacitors.
 In Sec.~\ref{sec:detailed_execution_model}, we demonstrate that understanding this model is critical for software designers:
 intermittent systems designed upon the traditional model can be up to 5.62x more energy-inefficient than expected and may fail to predict power-off timings accurately, leading to unsafe checkpointing. 
-In Sec.~\ref{sec:design_guidelines}, we propose design guidelines to implement efficient and safe intermittent systems with small energy storages, based on the insights from our model.
-Our proposed power failure prediction methods improve end-to-end execution latencies by 2.86x in dynamic and 3.04x in static checkpointing schemes on average, without incurring any additional overhead.
+In Sec.~\ref{sec:design_guidelines}, we propose design guidelines to implement efficient and safe intermittent systems with small energy storages, leveraging insights from our model.
+Our proposed power failure prediction methods improve end-to-end execution latencies by 3.04x in static and 2.86x in dynamic checkpointing schemes on average, without incurring additional overhead.

sections/Notes.tex

@@ -2,9 +2,4 @@
 
 Using traditional model~\cite{shuklaEnergy2024a,reymondEarlyBird2024}.
 
-Estimating the remaining energy using the energy storage voltage.
-Use energy storage voltage for checkpoint signal~\cite{zengReplayCache2021,balsamoHibernus2015,balsamoHibernus2016,bhattiHarvOS2017,jayakumarQUICKRECALL2014,maengSupporting2019,maengAdaptive2020}.
-
-Power failure injection (soft reset)~\cite{wuIntOS2024,yildizEfficient2023}.
-
-Interrupt using Vdd~\cite{balsamoHibernus2016}.
+Use energy storage voltage for checkpoint signal~\cite{zengReplayCache2021,balsamoHibernus2015,balsamoHibernus2016,bhattiHarvOS2017,jayakumarQUICKRECALL2014,maengSupporting2019,maengAdaptive2020}.

sections/OurApproach.tex

@@ -1,34 +1,61 @@
 \section{Design Guidelines}
 \label{sec:design_guidelines}
 
+Based on the insights from our model, we propose design guidelines for efficient and safe intermittent systems.
+The effectiveness of the guidelines is evaluated on seven benchmarks on the reference system used in Sec.~\ref{sec:detailed_execution_model}. 
+We ported five benchmarks from miBench~\cite{guthausMiBench2001} benchmark suite and implemented two computation kernels (\emph{matmul} and \emph{conv2d}) commonly used for evaluating intermittent systems in literature~\cite{kimLACT2024,maengSupporting2019,bhattacharyyaNvMR2022,ganesanWhat2019,akhunovEnabling2023}.
+
+We evaluate two popular existing checkpointing schemes: \emph{static} and \emph{dynamic}.
+The static scheme~\cite{} inserts checkpoint triggers at every loop latch in the program during compilation.
+At runtime, checkpoint triggers check the capacitor voltage and execute checkpoint only when it is below a predefined threshold.
+In contrast, the dynamic scheme~\cite{} does not modify the original program code.
+Instead, it executes checkpoints via interrupts from the power management system, generated when the power-off threshold is reached.
+All the evaluations are conducted with 470uF energy storage and 1mA of input current unless otherwise stated.
+
 \subsection{Delay Checkpoint Execution}
 
-The overhead of early checkpointing is considered small~\cite{choiCompilerDirected2022}.
-For example, some static checkpointing~\cite{bhattiHarvOS2017} and WCET-based approaches~\cite{choiCompilerDirected2022,reymondSCHEMATIC2024} have explored strategy that 
-WCET-based approaches can be extremely pessimistic~\cite{raffeckWoCA2024}.
+Delaying checkpoint execution until the last possible moment is generally regarded as desirable in existing works~\cite{bhattiHarvOS2017}. 
+However, this has not been considered a critical property, since early checkpoint execution makes the system wake up sooner, incurring only a small cost of initialization and recovery. 
+For example, some static checkpoint approaches have explored proactive power-offs based on the program's worst-case execution time~\cite{choiCompilerDirected2022,reymondSCHEMATIC2024}, which can be overly pessimistic~\cite{raffeckWoCA2024}.
+On the other hand, Our model reveals that significant energy is wasted each time the system powers off (Sec.~\ref{sec:power_efficiency}).
+As a result, the importance of delaying checkpoint executions is greater than previously assumed.
 
 \begin{figure}
     \centering
     \includegraphics[width=\linewidth]{figs/plot_expr_7_cropped.pdf}
     \caption{Execution times across various checkpoint voltages, normalized to the 3.4V case.}
-    % \label{fig:hardware_setup}
+    \label{fig:expr_checkpoint_voltages}
 \end{figure}
 
+Fig.~\ref{fig:expr_checkpoint_voltages} shows the benchmark execution times in dynamic checkpoint scheme, across various checkpoint execution voltages.
+A 1100uF capacitor is used and the execution times are normalized to the 3.4V case. 
+The figure shows that executing checkpoint earlier is considerably inefficient: 1.38x and 2.45x with 3.7V and 4.0V configurations, respectively.
+Consequently, it is important to execute as long as possible whenever the system wakes up.
+In the next section, we discuss how this can be implemented in the existing intermittent systems.
+
 \subsection{Use Vdd and Known Voltage for Checkpoint Execution}
 \label{sec:use_vdd}
 
 Sec.~\ref{sec:predicting_power_failures} demonstrates that capacitor voltage is not a good estimate for the system's remaining execution time.
-Instead, we propose using Vdd for accurate estimation for imminent power-off, as in works not having power management systems (Sec.~\ref{sec:related_work}).
-Also, utilize a voltage reference with a known value.
-Note that the reference voltage should be lower than the minimal operating voltage of MCU.
+Instead, we propose using Vdd to accurately estimate the imminent power-off, as in works that do not have the power management systems (Sec.~\ref{sec:related_work}).
+Also, when dealing with the Vdd, it is important to consider the operations of ADC in sub-normal voltage (Sec.~\ref{sec:sub_normal_execution}).
+For consistent operation of ADCs, the computing system needs a voltage source with a known value.
+In STM32L5 and MSP430, there exist internal reference voltage source of 1.2V; an external voltage reference~ (e.g., TI LVM431~\cite{texasinstrumentsLMV431}) can be considered otherwise.
+% Note that the reference voltage should be lower than the minimal operating voltage of MCU as it is regulated from Vdd.
 We propose two efficient implementations, each for dynamic and static checkpoint schemes.
 
-T1 utilizes a on-chip comparator (available both in STM32L5 and MSP430).
-Using a voltage divider with two resistors, Vdd is reduced so that the comparator is triggered when the target power-off voltage is reached.
+$T_{sta}$ is a setup for static checkpoint techniques, which poll the capacitor voltage and execute checkpoint only the voltage is below a threshold.
+Instead of reding the energy storage voltage, $T_{sta}$ reads the known voltage $V_{ref}$, which results in the same value of $\lfloor V_{ref}/V_{dd} \cdot 2^n \rfloor$ when operating on normal voltage.
+During sub-voltage execution, this value increases as $V_{dd}$ decreases.
+Given that the target threshold voltage for checkpoint execution is $V_{th}$, software designers can compare the ADC value with $\lfloor V_{ref}/V_{th} \cdot 2^n \rfloor$ to determine whether to execute checkpoint.
 
-T2 is setup for static checkpoint techniques, which poll the capacitor voltage to determine whether execute checkpoint or not.
-Instead of reading the capacitor voltage, it reads the reference voltage.
-As we discussed in Sec.~\ref{sec:sub_normal_execution}, the voltage remains same while the system executes at normal voltage but the value increases during sub-normal voltage execution.
+On the other hand, $T_{dyn}$ utilizes an on-chip comparator, which is available in most modern MCUs including STM32L5 and MSP430.
+As $V_{ref}$ is always lower than $V_{dd}$, we use a voltage divider using two resistors, $R1$ and $R2$, to reduce $V_{dd}$ and compare it with $V_{ref}$.
+Specifically, we set $R1$ and $R2$ to satisfy $\frac{R2}{R1+R2} \cdot V_{th} = V_{ref}$ so that the comparator generates an interrupt when $V_{dd}$ reaches the threshold voltage $V_{th}$.
+
+% T2 is setup for static checkpoint techniques, which poll the capacitor voltage to determine whether execute checkpoint or not.
+% Instead of reading the capacitor voltage, it reads the reference voltage.
+% As we discussed in Sec.~\ref{sec:sub_normal_execution}, the voltage remains same while the system executes at normal voltage but the value increases during sub-normal voltage execution.
 
 % \begin{itemize}
 %     \item T1 utilizes a on-chip comparator (available both in STM32L5 and MSP430) with a reference voltage.
@@ -38,18 +65,23 @@ As we discussed in Sec.~\ref{sec:sub_normal_execution}, the voltage remains same
 \begin{figure}
     \centering
     \begin{subfigure}{\linewidth}
-        \includegraphics[width=\textwidth]{figs/plot_expr_10_cropped.pdf}
-        \caption{Dynamic checkpointing (JIT).}
-        % \label{fig:eval_voltage_trace}
+        \includegraphics[width=\textwidth]{figs/plot_expr_11_cropped.pdf}
+        \caption{Static checkpointing with $T_{sta}$.}
+        \label{fig:expr_precise_checkpoint_timings_static}
         \vspace{7pt}
     \end{subfigure}
     \begin{subfigure}{\linewidth}
-        \includegraphics[width=\textwidth]{figs/plot_expr_11_cropped.pdf}
-        \caption{Static checkpointing.}
-        % \label{fig:eval_adaptivenss_finished_tasks}
+        \includegraphics[width=\textwidth]{figs/plot_expr_10_cropped.pdf}
+        \caption{Dynamic checkpointing with $T_{dyn}$.}
+        \label{fig:expr_precise_checkpoint_timings_dynamic}
     \end{subfigure}
     \caption{Impact of precise checkpoint timings to the end-to-end execution times.}
-    % \label{fig:sub_voltage_execution}
+    \label{fig:expr_precise_checkpoint_timings}
 \end{figure}
 
-\subsection{Design Checkpoint Techniques for Sufficient Power Duration}
+Fig.~\ref{fig:expr_precise_checkpoint_timings} shows 
+
+\subsection{Checkpoint Techniques and Evaluation Methods}
+% \subsection{Design Checkpoint Techniques for Sufficient Power Duration}
+
+Power failure injection (soft reset)~\cite{wuIntOS2024,yildizEfficient2023}.

sections/OurModel.tex

@@ -2,8 +2,8 @@
 \label{sec:detailed_execution_model}
 
 In this section, we describe our execution model and its implications for software design.
-In Sec.~\ref{sec:system_description}, we introduce target architecture and the reference system used for evaluations.
-Sec.~\ref{sec:execution_model} presents the proposed execution model, designed based on the key observations from experimental results.
+Sec.~\ref{sec:system_description} introduces the target architecture and the reference system used for evaluations.
+In Sec.~\ref{sec:execution_model}, we present the proposed execution model, derived from key observations obtained through experimental results.
 In the following three sections, we discuss how this model affects both the power efficiency and correctness of software design.
 Finally, in Sec.~\ref{sec:other_architectures}, we evaluate the effectiveness of our model across systems with different architectural configurations. 
 
@@ -22,14 +22,15 @@ The power management system is responsible for accumulating the incoming energy
 The computing system equips NVMs along with the MCU and peripherals, and utilize the NVMs for state retention between power failures.
 
 This setup includes two notable decoupling capacitors that affect the execution model of intermittent systems.
-The first one (C1 in the figure) is placed at the power management system as voltage regulators require a capacitor larger than the device-specific minimum capacitance for stable operation.
-Also, the computing system has its own decoupling capacitor (C2) to stabilize operating voltage.
+The first one (C1 in the figure) is located within the power management system as voltage regulators require a capacitor larger than the device-specific minimum to ensure stable operation.
+The second capacitor (C2) is part of the computing system and is used for stabilizing the operating voltage against sudden current draw.
 
-Recent studies increasingly explore 32-bit architectures for the computing system~\cite{shihIntermittent2024,wuIntOS2024,kimRapid2024,akhunovEnabling2023,kimLACT2024,kimLivenessAware2023,parkEnergyHarvestingAware2023,kortbeekWARio2022,khanDaCapo2023,barjamiIntermittent2024,songTaDA2024}, as emerging applications on intermittent systems, such as Deep Neural Networks (DNNs)~\cite{houTale2024,yenKeep2023,khanDaCapo2023,gobieskiIntelligence2019,islamEnabling2022,kangMore2022,leeNeuro2019,islamZygarde2020,custodeFastInf2024,barjamiIntermittent2024,songTaDA2024}, demand greater computational capabilities~\cite{bakarProtean2023a,carontiFinegrained2023}.
-In this context, we employ a custom-built board featuring a 32-bit ARM Cortex-M33 processor (STM32L5, operating at 16Mhz) with 512KB of Ferroelectric RAM (FRAM) as a reference system.
-A TI BQ25570 based board is used for the power management system, with power-on and off thresholds of 4.9V and 3.4V, respectively.
+Recent studies have increasingly explored 32-bit architectures for computing systems~\cite{shihIntermittent2024,wuIntOS2024,kimRapid2024,akhunovEnabling2023,kimLACT2024,kimLivenessAware2023,parkEnergyHarvestingAware2023,kortbeekWARio2022,khanDaCapo2023,barjamiIntermittent2024,songTaDA2024}, as emerging applications on intermittent systems, such as Deep Neural Networks (DNNs)~\cite{houTale2024,yenKeep2023,khanDaCapo2023,gobieskiIntelligence2019,islamEnabling2022,kangMore2022,leeNeuro2019,islamZygarde2020,custodeFastInf2024,barjamiIntermittent2024,songTaDA2024}, demand greater computational capabilities~\cite{bakarProtean2023a,carontiFinegrained2023}.
+In this context, we employ a custom-built board featuring a 32-bit ARM Cortex-M33 processor (STM32L5, operating at 16Mhz) with 512KB of Ferroelectric RAM (FRAM) as our reference system.
+For the power management system, we use a TI BQ25570-based board with power-on and power-off thresholds of 4.9 V and 3.4 V, respectively.
+% A TI BQ25570 based board is used for the power management system, with power-on and off thresholds of 4.9V and 3.4V, respectively.
 We empirically select 22uF and 220uF capacitors for C1 and C2, respectively, as these are the minimum capacitor sizes for stable checkpoint and recovery.
-Sec.~\ref{sec:other_architectures} evaluates generality of our model in different architectures, such as systems with Magnetic RAM (MRAM) and a 16-bit core (e.g., MSP430).
+Sec.~\ref{sec:other_architectures} evaluates the generality of our model across different architectures, such as systems with Magnetic RAM (MRAM) and a 16-bit core (e.g., MSP430).
 
 % In this work, our goal is to model the buffering effects of these capacitors and evaluate their implications on software designs.
 % (Recent studies present the need for better computing capability~\cite{bakarProtean2023a})
@@ -58,19 +59,19 @@ Sec.~\ref{sec:other_architectures} evaluates generality of our model in differen
 \end{figure}
 
 To derive general execution model with the effects of decoupling capacitors, we first present a sample measurement from our reference system.
-To generate operation time of 50ms under 1.5mA current supply, we use a 470uF capacitor for energy storage.
-Fig.~\ref{fig:execution_trace_one_cycle} shows the traces of the energy storage voltage and the MCU operating voltage (Vdd) for one power cycle.
+To achieve an operation time of 50ms under 1.5mA current supply, we use a 470uF capacitor for energy storage.
+Fig.~\ref{fig:execution_trace_one_cycle} illustrates the voltage traces of the energy storage and the MCU operating voltage (Vdd) over a single power cycle.
 Note that Vdd is maintained by decoupling capacitors after current supply from the power management system stops.
-The shaded areas represent the ranges that system executes the application code.
+The shaded areas represent the periods that system executes the application code.
 % Fig.~\ref{fig:execution_trace_one_cycle} shows the trace during one power cycle, and Fig.~\ref{fig:execution_trace_detailed} presents the first execution cycle in more detail.
 
 Fig.~\ref{fig:execution_trace_detailed} presents the first execution cycle in more detail. It shows several interesting differences between the traditional execution model and the actual operation.
-Among them, we highlight three key observations that affect software designer's decision.
+Among them, we highlight three key observations that affect software design decisions.
 
 \begin{itemize}
-    \item \textbf{O1}: The capacitor voltage drops quickly to charge decoupling capacitor when the system wakes-up ($t1$--$t2$).
-    \item \textbf{O2}: The system executes at sub-voltage using the decoupling capacitors, even after power supply stops ($t4$--$t5$).
-    \item \textbf{O3}: Decoupling capacitors discharge while the system is powered-off (after $t5$, as shown in Fig.~\ref{fig:execution_trace_one_cycle}).
+    \item \textbf{O1}: The capacitor voltage drops rapidly to charge decoupling capacitor when the system wakes up ($t1$--$t2$).
+    \item \textbf{O2}: The system operates at sub-voltage using the decoupling capacitors, even after power supply stops ($t4$--$t5$).
+    \item \textbf{O3}: Decoupling capacitors discharge while the system is powered off (after $t5$, as shown in Fig.~\ref{fig:execution_trace_one_cycle}).
 \end{itemize}
 
 \begin{figure}
@@ -82,23 +83,23 @@ Among them, we highlight three key observations that affect software designer's
 
 % As we discuss in the following sections, all three observations significantly impact the performance of intermittent system designs.
 % We propose a detailed execution model which reflects these observations.
-Fig.~\ref{fig:detailed_execution_model} shows our detailed execution model, which reflects these key observations.
-When the capacitor voltage reaches the power-on threshold, the voltage experience quick drop due to the buffering effects (\circled{1}), instead of gradual reduction.
-After initialization (\circled{2}), the system starts to execute at normal voltage (\circled{3}), 3.3V for example.
-When the voltage hits the power-off threshold, the power supply stops but system now starts to execute using the buffered energy (\circled{4}).
-Since voltage of the decoupling capacitor decreases as it discharges, the system executes at sub-normal voltage until it reaches the voltage it cannot operate (e.g., 2.5V).
+Fig.~\ref{fig:detailed_execution_model} illustrates our detailed execution model, incorporating these key observations.
+When the capacitor voltage reaches the power-on threshold, the voltage experience a rapid drop due to the buffering effects (\circled{1}), instead of gradual decline.
+After initialization (\circled{2}), the system begins execution at normal operating voltage (\circled{3}), 3.3V for example.
+When the voltage hits the power-off threshold, the power supply stops but system now starts to operate using the buffered energy (\circled{4}).
+Since the voltage of the decoupling capacitor decreases as it discharges, the system executes at sub-normal voltage until it reaches the voltage it cannot operate (e.g., 2.5V).
 % This voltage is known as Brown-Out Reset (BOR) voltage and is typically in a range of 1.7V to 2.5V in modern MCUs~\cite{}.
-Finally, until the next power-on, the remaining energy in decoupling capacitors continues to discharge (\circled{5}).
+Finally, until the next power-on event, the remaining energy in decoupling capacitors continues to discharge (\circled{5}).
 
-When designing intermittent systems, especially targeting small capacitors, it is important for software designers to understand this model.
-In the following sections, we discuss the impact of this model to software design in more detail.
+When designing intermittent systems, particularly those utilizing small capacitors, it is important for software designers to have clear understanding of this model.
+In the following sections, we discuss the impact of our model to software design in more detail.
 
 \subsection{Impact on Power Efficiency}
 \label{sec:power_efficiency}
 
 The traditional model implies that the energy consumed between power-on and power-off thresholds are entirely used in the computing system.
 However, our model reveals that considerable energy is used for charging the decoupling capacitors (\textbf{O1}) and dissipated during power-off durations (\textbf{O3}).
-This implies that much smaller energy may be used for the useful computation compared to the designer's expectation.
+This indicates that much smaller energy may be used for the useful computation compared to the designer's expectation.
 
 \begin{figure}
     \centering
@@ -107,17 +108,19 @@ This implies that much smaller energy may be used for the useful computation com
     \label{fig:power_distribution}
 \end{figure}
 
-Fig.~\ref{fig:power_distribution} shows the distribution of the energy consumed for each stage of operation within one power cycle, averaged over 50 executions, where 1mA of input current is provided at 1.9V.
-The x-axis represents different capacitor sizes and the line in the secondary axis represents the average operation times for application code.
+Fig.~\ref{fig:power_distribution} shows the distribution of the energy consumption for each stage of operation within one power cycle, averaged over 50 executions, where 1mA of input current is provided at 1.9V.
+The x-axis represents capacitor sizes and the line in the secondary axis represents the average operation times for application code.
 The checkpoint is executed by the interrupt from the power management system~\cite{}, which is generated when the capacitor voltage reaches the power-off threshold (3.4V).
 Note that this is the most efficient point for checkpoint execution according to the traditional model.
 
 The results shows that significant energy is wasted in the decoupling capacitors.
 For example, 60.7\% of power is wasted during the power-off duration (denoted as \emph{Dischrged}) in 470uF case.
-The discharging behavior can be modeled as RC-discharging circuit (i.e., $q=CVe^{-\frac{1}{RC}t}$), which has exponential discharge rate.
-As a result, the cost from discharging is more expensive when the capacitor size is small;
-in our case, 50\% of energy is discharged at the first 161 ms.
-The discharge rate decreases as the capacitor size increases, down to 28.5\% in 1320uF case, which is still not negligible.
+The discharging behavior can be modeled as an RC-discharging circuit (i.e., $q=CVe^{-\frac{1}{RC}t}$), which exhibits an exponential discharge rate.
+As a result, the energy loss due to discharging is more expensive when the capacitor size is small.
+In our case, 50\% of energy is discharged within the first 161 ms.
+While the discharge rate decreases with larger capacitor sizes, it remains significant;
+for example, in the 1320uF case, 28.5\% of energy is discharged, which is still non-negligible.
+% The discharge rate decreases as the capacitor size increases, down to 28.5\% in 1320uF case, which is still not negligible.
 % The cost is more expensive when the capacitor size is small since the discharge rate follows the RC-discharging circuits.
 % While using smaller capacitors shortens the power-off durations, the discharging behavior penalizes them most since RC-discharging circuits discharge exponentially (in our case, 50\% of energy is discharged at the first 161 ms).
 % As a result, 60.7\% of power is wasted in 470uF, and the rate decreases as the capacitor size increases, down to 28.5\% in 1320uF case.
@@ -125,10 +128,10 @@ The discharge rate decreases as the capacitor size increases, down to 28.5\% in
 Another important observation is the error introduced by the traditional model.
 The traditional model expects both the energies, \emph{Execution} and \emph{Discharged}, are used for computation.
 This introduces significant errors, up to 5.62x in 470uF setup.
-In the same context, the traditional model expects using 470uF capacitor instead of 1320uF results in merely 1.22x overhead in energy efficiency, but the actual energy efficiency differs by 4.71x.
+In the same context, the traditional model predicts that using a 470uF capacitor instead of a 1320uF would result in only 1.22x overhead in energy efficiency, while the actual difference is 4.71x.
 % However, our model shows that the actual energy efficiency differs by xx\% in reality, brining xx\% error in the traditional model.
-This can significantly mislead the system designers when they decide the capacitor size by considering tradeoffs between overall efficiency and reactiveness.
-In Sec.~\ref{sec:design_guidelines}, we discuss options to minimize overhead from discharging when designing software techniques.
+This can significantly mislead system designers when they select capacitor sizes by considering tradeoffs between overall efficiency and reactiveness.
+In Sec.~\ref{sec:design_guidelines}, we explore strategies to minimize overhead caused by discharging when designing software techniques.
 
 % More importantly, this wasted energy is expected to be used for the computation in traditional execution model, as all the energy except for the initialization and checkpoint/recovery is expected to be used in computations.
 % It brings significant errors between the two models in available energy for the execution.
@@ -141,13 +144,13 @@ In Sec.~\ref{sec:design_guidelines}, we discuss options to minimize overhead fro
 \subsection{Impact on Predicting Power Failures}
 \label{sec:predicting_power_failures}
 
-According to the traditional model, the system states should be saved to NVM before power-off threshold, as the system halts at this point.
-On the other hand, our model shows that the system may operate afterward using the energy stored in the decoupling capacitors (\textbf{O2}). 
-Since modern MCUs can operate on a range of supply voltages (e.g., from 1.7V to 3.6V in STM32L5 and MSP430), the computing system is executed until the voltage of decoupling capacitors reaches the minimum operating voltage.
+According to the traditional model, system states should be saved to NVM before reaching power-off threshold, as the system halts at this point.
+On the other hand, our model shows that the system may continue operating using the energy stored in the decoupling capacitors (\textbf{O2}). 
+Since modern MCUs can operate across a wide range of supply voltages (e.g., from 1.7V to 3.6V in STM32L5 and MSP430), the computing system is executed until the voltage of decoupling capacitors drops to the minimum operating level.
 % Modern MCUs can operate on a range of supply voltages (e.g., from 1.7V to 3.6V for STM32L5 and MSP430).
 % Since the voltage of decoupling capacitors decreases as the discharge, the computing system is executed until the voltage reaches the minimum operating voltage.
 % While the voltage of decoupling capacitors decreases as they discharge, the computing system operates since modern MCUs can operate on a range of supply voltages (e.g., from 1.7V to 3.6V for STM32L5 and MSP430).
-This makes the energy storage voltage not a good estimate of the remaining time that system can execute.
+This makes the energy storage voltage not a reliable estimate of the remaining execution time.
 
 \begin{figure}
     \centering
@@ -168,34 +171,35 @@ This makes the energy storage voltage not a good estimate of the remaining time
 
 % Modern MCUs can operate on wide range of operating voltages (e.g., from 1.7V to 3.6V for STM32L5 and MSP430).
 
-Fig.~\ref{fig:sub_voltage_execution} shows the ratio of the times executed under sub-voltage over the total execution times, averaged over 30 measurements.
-The x-axis shows the different capacitor sizes and the colors represent the voltages that system stops its operation.
-We evaluate various voltages ranging from 1.7V to 2.5V since not all components in the computing system may operate at the lowest voltage (Sec.~\ref{sec:sub_normal_execution}).
-Also, we present two different cases with input current of 1mA (Fig.~\ref{fig:sub_voltage_execution_1mA}) and 3mA (Fig.~\ref{fig:sub_voltage_execution_3mA}) to evaluate the impact of input power.
+Fig.~\ref{fig:sub_voltage_execution} presents the ratio of the times executed under sub-voltage to the total execution times, averaged over 30 measurements.
+The x-axis represents different capacitor sizes and the colors indicate the voltage levels at which the system stops operation.
+We evaluate a range of stop voltages from 1.7V to 2.5V since not all components in the computing system may function at the lowest voltage (Sec.~\ref{sec:sub_normal_execution}).
+Also, we examine two cases with different input currents of 1mA (Fig.~\ref{fig:sub_voltage_execution_1mA}) and 3mA (Fig.~\ref{fig:sub_voltage_execution_3mA}), to assess the impact of varying input power.
 
-The figure shows that significant MCU operation is executed at sub-normal voltage.
-For example, when 470uF capacitor is used at 1mA input current (Fig.~\ref{fig:sub_voltage_execution_1mA}), 82.8\% of computation is executed \emph{after} power-off threshold.
-The ratio decreases as the system powers-off early (reduced sub-voltage operation time) or the input current increases (longer operation time at normal voltage).
+The figure shows that a significant portion of MCU operation occurs at sub-normal voltage.
+For example, when 470uF capacitor is used at 1mA input current (Fig.~\ref{fig:sub_voltage_execution_1mA}), 82.8\% of computation takes place \emph{after} the power-off threshold.
+This ratio decreases as the system powers off earlier (reducing sub-voltage operation time) or the input current increases (extending operation time at normal voltage).
 Under 1000uF is the major focus of this paper.
 
-These values can be directly translated to the inefficiency of the system based on the traditional model.
-For example, in 470uF with 1mA input current case, systems executing checkpoint at power-off threshold may operate 16.3ms, although it can operate 29.4ms longer if it execute checkpoint at 2.5V.
-At next power-on, decoupling capacitors are discharged to similar voltages in either cases, as capacitors discharge exponentially (Sec.~\ref{sec:power_efficiency}).
-As a result, failing to execute at sub-normal voltage introduces significant power efficiency overhead.
+These values can be directly translated to the inefficiencies of the system based on the traditional model.
+For example, in the case of 470uF with 1mA input current, systems executing checkpoint at power-off threshold may operate 16.3ms.
+However, the system could operate for an additional 29.4ms if the checkpoint is executed at 2.5V.
+At the next power-on, the decoupling capacitors discharge to similar voltage levels in both cases, as their discharge behavior follows an exponential curve (Sec.~\ref{sec:power_efficiency}).
+As a result, failing to utilize the available energy at sub-normal voltage introduces significant power efficiency overhead.
 % Although early checkpoint execution may save some energy in decoupling capacitors, the saved energy is not preserved as discussed in Sec.~\ref{sec:power_efficiency}.
-In Sec.~\ref{sec:design_guidelines}, we validate this aspect and propose a method to predict the power-off time more accurately.
+In Sec.~\ref{sec:design_guidelines}, we validate this aspect and propose methods to predict the power-off time more accurately.
 
 \subsection{Impact of Sub-normal Voltage Execution}
 \label{sec:sub_normal_execution}
 
-The traditional model makes the software designers assume the system is executed under stable voltage.
-However, the majority of execution may happen after the power-off threshold at sub-normal voltage (\textbf{O3}), as discussed in Sec.~\ref{sec:predicting_power_failures}.
-Being aware of this is important to software designers since the peripherals and analog components may function differently at sub-normal voltage.
+The traditional model leads the software designers to assume that the system is executed under a stable voltage.
+However, a significant portion of execution may happen after the power-off threshold at sub-normal voltage (\textbf{O3}), as discussed in Sec.~\ref{sec:predicting_power_failures}.
+Being aware of this is crucial to software designers since the peripherals and analog components may function differently at sub-normal voltage.
 
-The two most relevant examples are Analog-Digital Converters (ADCs) and external NVMs.
-They play an important role in checkpointing, since ADCs are often used to estimate power-off time by reading the capacitor voltage and NVM is the checkpoint storage itself.
-At the same time, they are likely executed at sub-normal voltage as checkpoint is executed just before the power-off.
-Incorrect execution of these components may lead to unsafe or incomplete checkpoint executions.
+Two of the most relevant examples are Analog-Digital Converters (ADCs) and external NVMs.
+They play an important role in checkpointing, since ADCs are often used to estimate power-off time by reading the capacitor voltage and NVM serves as the storage for checkpoints.
+At the same time, they are likely to operate at sub-normal voltages, as it is most efficient to execute checkpoint just before power-off.
+% Incorrect execution of these components may lead to unsafe or incomplete checkpoint executions.
 
 \begin{figure}
     \centering
@@ -215,16 +219,17 @@ Incorrect execution of these components may lead to unsafe or incomplete checkpo
 \end{figure}
 
 Fig.~\ref{fig:adc_error} shows the behavior of ADCs in sub-normal voltage.
-ADC quantizes the input analog voltage into the range of discrete $n$ values from 0 to $V_{ref}$, where $n$ is a resolution and $V_{ref}$ is a reference voltage.  
-As STM32L5 uses Vdd as reference voltage, accessing ADC during sub-normal voltage operation results in inconsistent results.
-As shown in the figure, it returns larger values than the measurements since the range ADC can represent is decreased as Vdd decreases.
-As a result, during sub-normal voltage operation, the system may believe there is sufficient energy from the ADC results and decide not to execute checkpoint.
-
-Also, some peripherals may not work below certain voltage.
-Fig.~\ref{fig:fram_drror} presents the error rate of FRAM in the reference system at different voltages, showing FRAM cannot operate correctly when the voltage is below 2.4V.
-Since the system operates until it reaches the lowest MCU operation voltage (e.g., 1.7V), software designers should guarantee that peripherals are accessed at safe voltage.
-In our reference system, failing to this may result in corrupted or incomplete checkpointing.
-In Sec.~\ref{sec:design_guidelines}, we propose two techniques that can safely estimate the power-off time under sub-normal voltage.
+ADC quantizes the input analog voltage into the range of discrete $2^n$ values from 0 to $V_{ref}$, where $n$ is a resolution and $V_{ref}$ is a reference voltage, and cannot read the input voltage larger than $V_{ref}$.  
+As STM32L5 is designed to use Vdd as reference voltage, accessing the ADC during sub-normal voltage operation leads to inconsistent results.
+As shown in the figure, the ADC returns values higher than the measurements since ADC representation range is decreased as Vdd drops.
+As a result, during sub-normal voltage operation, the system may incorrectly interpret ADC results as there is sufficient energy and decide not to execute a checkpoint.
+
+Also, intermittent systems typically designed with the use of peripherals, including sensors~\cite{yildizAdaptable2024,dangIoTree2022,afanasovBatteryless2020,maengAdaptive2020}, wireless communication modules~\cite{katanbafMultiScatter2021,dewinkelIntermittentlypowered2022,babatundeGreentooth2024} or external NVMs~\cite{dewinkelIntermittentlypowered2022,kimLACT2024,kimLivenessAware2023,akhunovEnabling2023}, which have their own minimum operating voltage requirements.
+% Also, some peripherals may not work below certain voltage.
+Fig.~\ref{fig:fram_drror} illustrates the error rate of FRAM in the reference system at different voltages, showing FRAM cannot operate reliably below 2.4V.
+Since the system continues operating until it reaches the lowest MCU operation voltage (e.g., 1.7V), software designers must ensure that peripherals are accessed only at safe voltage levels.
+Failing to this can result in corrupted data or incomplete checkpointing.
+In Sec.~\ref{sec:design_guidelines}, we propose two techniques that can safely estimate the power-off time under sub-normal voltage conditions.
 
 \subsection{Sensitivity to Architectural Designs}
 \label{sec:other_architectures}
@@ -250,12 +255,12 @@ In Sec.~\ref{sec:design_guidelines}, we propose two techniques that can safely e
     }
     \end{table}
 
-To evaluate the generality of our model, we employ two additional architectural setups.
-Table~\ref{tab:architectures} shows the detailed parameters of them.
-A1 is the same setup with the reference system but equips MRAM (Everspin MR5A16ACYS35) instead of FRAM.
-This setup is evaluated as MRAM is also gaining attention as a next generation NVM~\cite{akhunovEnabling2023,bakarProtean2023a,dewinkelIntermittentlypowered2022,wuIntOS2024}.
-Second target is MSP430, which has been most popular 16-bit platform in intermittent system research.
-For both systems, we set architectural parameters to make operation time around 50ms.
+To verify generality of our model, we evaluate it using two additional architectural setups.
+Table~\ref{tab:architectures} shows the detailed parameters of the target architectures.
+A1 shares the same configuration as the reference system but equips MRAM (Everspin MR5A16ACYS35) instead of FRAM.
+This setup is included since MRAM is also gaining attention as a next generation NVM~\cite{akhunovEnabling2023,bakarProtean2023a,dewinkelIntermittentlypowered2022,wuIntOS2024}.
+Second target is the MSP430, which has been the mostly adopted 16-bit platform in intermittent system research.
+For both systems, the architectural parameters are set to achieve an operation time of approximately 50 ms.
 
 \begin{figure}
     \centering
@@ -264,11 +269,14 @@ For both systems, we set architectural parameters to make operation time around
     \label{fig:other_architectures}
 \end{figure}
 
-Fig.~\ref{fig:other_architectures} shows the results in different power-off voltage.
-The bar in the left side shows the energy breakdown in one power cycle, and the one in the right side represents the ratio of the execution time operated at sub-voltage.
-The most noticeable difference is ratio of energy consumed for ramp-up and init.
-While A1 consumes 63.4\% power at this stage on average, A2 consumes only 5.6\%.
-This is because A1 shows larger leakage current due to external MRAM, which consumes more current than FRAM in our case.
-However, both architectures show high sub-voltage execution rates, up to 70.1\% in A2.
-In addition, discharged energy takes considerable portion both in A1 (31.4\%) and A2 (52.0\%) at 3.3V configuration, which represents the techniques based on the traditional model.
-In summary, the evaluation reveals that the buffering effect of system's capacitance and its implications are general in other systems.
+Fig.~\ref{fig:other_architectures} shows the results for different power-off voltages.
+The bars on the left illustrate the energy breakdown in a single power cycle, and the bars on the right represent the ratio of the execution time operated at sub-voltage.
+The most noticeable difference is ratio of energy consumed during the ramp-up and init stage.
+While A1 consumes 63.4\% power at this stage on average, only 5.6\% of energy is consumed in A2.
+This is because A1 is configured to use external MRAM, which exhibits significantly higher leakage current than FRAM used in the reference system.
+In contrast, MSP430 (A2) is equipped with on-chip FRAM, which has much lower leakage.
+
+Despite these differences, both architectures exhibit high sub-voltage execution rates, up to 55.5\% in A1 and 70.1\% in A2.
+In addition, discharged energy takes considerable portion in both A1 (31.4\%) and A2 (52.0\%) at 3.3V power-off voltage configuration, which represents the techniques based on the traditional model that halt immediately at power-off threshold.
+In summary, the evaluation demonstrates that the modeled buffering effects are general and their impacts are significant across different system architectures.
+% In summary, the evaluation reveals that the buffering effect of system's capacitance and its implications are general in other systems.

sections/RelatedWork.tex

@@ -1,15 +1,14 @@
 \section{Related Work}
 \label{sec:related_work}
 
-Techniques to find the best hardware configurations (model approaches~\cite{kimRapid2024,houTale2024,erataETAP2023,ghasemiPES2023,sanmiguelEH2018a,sanmiguelEH2018}).
-Tradeoff of capacitor size and forward progress~\cite{zhanExploring2022}.
-These works do not consider discharge of decoupling capacitor.
-
-In the works not having dedicated power management system~\cite{balsamoHibernus2015,balsamoHibernus2016,netoDiCA2023,raffeckCO2CoDe2024,reymondEarlyBird2024}, 
-
-Considering sub-normal voltage execution~\cite{zhanExploring2022}.
-In transient computing~\cite{balsamoHibernus2015,balsamoHibernus2016,netoDiCA2023,raffeckCO2CoDe2024} (works do not using separate power management system) or hardware-based approaches.
-This work shows that considering sub-normal voltage execution is also important for designs using separate energy management system.
-They do not address the impact of sub-normal voltage execution to correctness and efficiency of software designs.
-
-Checkpoint techniques using capacitor voltage as an estimate of available energy.
+This work can be compared to the existing modeling-based approaches that estimate the latency or efficiency of the intermittent systems~\cite{kimRapid2024,houTale2024,erataETAP2023,ghasemiPES2023,sanmiguelEH2018a,sanmiguelEH2018}.
+The primary focus of these works is to find the most efficient design configurations (e.g., capacitor size, input power or checkpoint techniques~\cite{kimRapid2024}) for the given application.
+Zhan et al.~\cite{zhanExploring2022} especially focused on the tradeoff of capacitor size and the forward progress.
+However, the modelings in these works assume the entire energy discharged in the capacitor is used in the computing systems, overlooking the buffering effects that are addressed in this work.
+Furthermore, this work propose several practical guidelines that can improve the efficiency of the existing techniques with minimal efforts.
+
+In some works that do not have a dedicated power management system and directly supply unregulated power to the computing system~\cite{balsamoHibernus2015,balsamoHibernus2016,netoDiCA2023,raffeckCO2CoDe2024,reymondEarlyBird2024}, the MCU operating voltage (Vdd) has been used for checkpoint signals.
+This is natural in these works since the voltage of the energy storage is always same as Vdd and the MCU operates in varying voltage levels.
+On the other hand, our work demonstrates that considering sub-normal voltage operation is also important in the systems with a regulated power supply, which is the majority.
+% Especially, this work reveals that these impacts come from the buffering effects of the inherent capacitance, which are not exist in these works.
+Also, we address the impacts of sub-normal voltage execution to correctness and efficiency of software designs, along with the suggestions to exploit such impacts.