Update on local

IEEE-conference-template-062824.tex

@@ -13,8 +13,7 @@
 \usepackage{subcaption}
 \begin{document}
 
-% \title{Intermittent Systems with Small Scale: Model and Design Guidelines \\
-\title{Intermittent Systems in Small Scale: Execution Model and Design Guidelines \\
+\title{Intermittent Systems at Small Scale: Execution Model and Design Guidelines \\
 \thanks{This work was supported by IITP grant funded by the Korea government (MSIT) (No.2021-0-00360, Development of Core Technology for Autonomous Energy-driven Computing System SW in Power-instable Environment).}
 }
 
@@ -27,11 +26,16 @@ Electronics and Telecommunications Research Institute (ETRI), Daejeon, Republic
 \maketitle
 
 \begin{abstract}
-    Abstract.
+    Intermittent systems enable the execution of long-running tasks in environment with frequent power failures.
+    When designing such systems, software designers rely on execution models that abstract operations in hardware and describe how intermittent systems function.  
+    However, as recent techniques explore very short operation times with smaller energy storages, traditional models no longer provide precise abstractions of the real hardware behavior.
+    In this paper, we propose a detailed execution model that considers buffering effects of system's inherent energy storage components.
+    Our evaluation shows that intermittent systems designed without accounting for these effects can be up to 4.99x less power efficient and may lead to unsafe checkpoint execution.
+    Furthermore, our design guidelines improve end-to-end latency of applications in dynamic and static checkpoint techniques by 2.86x and 3.04x, respectively, without incurring any extra overhead. 
 \end{abstract}
 
 \begin{IEEEkeywords}
-keywords.
+Intermittent Computing, Batteryless System.
 \end{IEEEkeywords}
 
 \input{sections/Introduction.tex}

sections/Introduction.tex

@@ -24,7 +24,7 @@ Software designers aim to leverage this execution model to implement intermitten
 \end{figure}
 
 
-In the meantime, researches on intermittent systems are increasingly exploring shorter operation time by using smaller capacitors.
+In the meantime, researches on intermittent systems are increasingly exploring shorter operation time by using smaller capacitors (e.g., less than 1mF~\cite{ahmedEfficient2019}).
 Operate on small capacitors is generally desirable, as it not only reduces device volume but also enhances the responsiveness by enabling the system to wake up more frequently~\cite{bakarProtean2023a,maengAdaptive2020,alsubhiStash2024}.
 As a result, recent studies have targeted operation times in the range of tens of milliseconds~\cite{reymondSCHEMATIC2024,wuIntOS2024,yildizEfficient2023,choiCompilerDirected2022} or even microseconds~\cite{reymondSCHEMATIC2024,wuIntOS2024}.
 However, as energy storage size decreases, the traditional execution model no longer provides an accurate abstraction of actual execution behavior.
@@ -37,7 +37,7 @@ However, their buffering effect introduces discrepancies between the execution m
 For example, when the system powers on, decoupling capacitors are quickly charged using the energy in the storage, making the energy storage voltage an unreliable estimate of available energy.
 This buffered energy also allows the system operate for a while at a sub-normal voltage after the power supply is stopped.
 Additionally, between power cycles, decoupling capacitors discharge due to the resistance of the system, which significantly lowers the power efficiency.
-In systems with small capacitors, these effects dominate the behaviors modeled in the traditional model.
+In the systems with small capacitors, these effects dominate the behaviors that modeled in the traditional model.
 Consequently, techniques that are highly efficient according to the traditional model may introduce substantial power overhead and even correctness issues in small-scale systems.
 % Consequently, designing software techniques based on the traditional model brings significant power overhead and even correctness issues, even they are extremely efficient in the traditional model.
 % While this seems merely delaying the start and the end of the operations at first glance, we will show that it significantly affects the power efficiency and even correctness of software designs.

sections/OurModel.tex

@@ -1,8 +1,8 @@
 \section{Detailed Intermittent Execution Model}
 
-In this Section, we provide a detailed description of our execution model for intermittent systems and its implications for software design.
-In Sec.~\ref{sec:system_description}, we introduce the target hardware setup of our model and the reference system used for evaluations.
-Sec.~\ref{sec:execution_model} presents our proposed execution model, designed based on the key observations from our measurements.
+In this Section, we provide a detailed description of our intermittent system execution model and its implications for software design.
+In Sec.~\ref{sec:system_description}, we introduce the target architecture of our model and the reference system used for evaluations.
+Sec.~\ref{sec:execution_model} presents our detailed execution model, designed based on the key observations from our experimental results.
 In the following three sections, we discuss how this model affects both the power efficiency and correctness of software design.
 Finally, in Sec.~\ref{sec:other_architectures}, we evaluate the effectiveness of our model across systems with different architectural configurations. 
 
@@ -24,12 +24,12 @@ This setup includes two notable decoupling capacitors that affect the execution
 The first one (C1 in the figure) is placed at the power management system as voltage regulators require a capacitor larger than the device-specific minimum capacitance for stable operation.
 Also, the computing system has its own decoupling capacitor (C2) to stabilize operating voltage.
 
-Recent studies increasingly consider use of 32-bit architectures for the computing system~\cite{shihIntermittent2024,wuIntOS2024,kimRapid2024,akhunovEnabling2023,kimLACT2024,kimLivenessAware2023,parkEnergyHarvestingAware2023,kortbeekWARio2022,khanDaCapo2023}, as emerging applications on intermittent systems, such as DNNs~\cite{houTale2024,yenKeep2023,khanDaCapo2023,gobieskiIntelligence2019,islamEnabling2022a,kangMore2022,leeNeuro2019,islamZygarde2020}, demand more computing capability~\cite{bakarProtean2023a,carontiFinegrained2023}.
+Recent studies increasingly explore 32-bit architectures for the computing system~\cite{shihIntermittent2024,wuIntOS2024,kimRapid2024,akhunovEnabling2023,kimLACT2024,kimLivenessAware2023,parkEnergyHarvestingAware2023,kortbeekWARio2022,khanDaCapo2023,barjamiIntermittent2024,songTaDA2024}, as emerging applications on intermittent systems, such as Deep Neural Networks (DNNs)~\cite{houTale2024,yenKeep2023,khanDaCapo2023,gobieskiIntelligence2019,islamEnabling2022,kangMore2022,leeNeuro2019,islamZygarde2020,custodeFastInf2024,barjamiIntermittent2024,songTaDA2024}, demand greater computational capabilities~\cite{bakarProtean2023a,carontiFinegrained2023}.
 % Emerging intermittent applications demand increasing computing capability~\cite{bakarProtean2023a} due to computat
-To this end, we use a custom-built board equipped with an ARM Cortex-M33 (operating at 16Mhz) and 512KB of FRAM as a reference system in this section.
-For power management system, we use TI BQ25570 based system.
-We empirically choose XXuF and 220uF capacitors for C1 and C2, respectively, as these are the minimum capacitor sizes for stable execution of checkpoint and recovery.
-For generality, Sec.~\ref{sec:other_architectures} evaluates our model in different architectures, such as systems with MRAM and 16-bit core.
+In this context, we employ a custom-built board featuring a 32-bit ARM Cortex-M33 processor (operating at 16Mhz) with 512KB of FRAM as a reference system.
+For the power management system, we use a TI BQ25570 based system.
+We empirically select XXuF and 220uF capacitors for C1 and C2, respectively, as these are the minimum capacitor sizes for stable checkpointing and recovery.
+Sec.~\ref{sec:other_architectures} evaluates generality of our model in different architectures, such as systems equipped with MRAM and a 16-bit core.
 
 % In this work, our goal is to model the buffering effects of these capacitors and evaluate their implications on software designs.
 % (Recent studies present the need for better computing capability~\cite{bakarProtean2023a})
@@ -44,31 +44,36 @@ For generality, Sec.~\ref{sec:other_architectures} evaluates our model in differ
     \centering
     \begin{subfigure}{\linewidth}
         \includegraphics[width=\textwidth]{figs/plot_expr_8a_cropped.pdf}
-        \caption{Trace of one power cycle.}
+        \caption{Voltage traces for one power cycle.}
         \label{fig:execution_trace_one_cycle}
         \vspace{5pt}
     \end{subfigure}
     \begin{subfigure}{\linewidth}
         \includegraphics[width=\textwidth]{figs/plot_expr_8b_cropped.pdf}
-        \caption{Detailed trace.}
+        \caption{Voltage traces around the first power-on.}
         \label{fig:execution_trace_detailed}
     \end{subfigure}
-    \caption{Voltage measurement of capacitor and Vdd (470uF, 1.5mA current supply).}
+    \caption{Voltages trace of energy storage and Vdd.}
     \label{fig:execution_trace}
 \end{figure}
 
-Fig.~\ref{fig:execution_trace} shows the voltage trace of the energy storage and the Vdd of the computing system.
-A 470uF capacitor is used for the energy storage to generate execution of about 50 ms under 1.5mA current supply.
-Fig.~\ref{fig:execution_trace_one_cycle} shows the trace during one power cycle, and Fig.~\ref{fig:execution_trace_detailed} presents the first execution cycle in more detail.
+To derive general execution model with the effects of decoupling capacitors, we first present a sample measurement in our reference system.
+To generate operation time of 50ms under 1.5mA current supply, we use a 470uF capacitor for the energy storage.
+Fig.~\ref{fig:execution_trace_one_cycle} shows the voltage trace of the energy storage and the operating voltage (Vdd) of the computing system for one power cycle.
+Note that Vdd is maintained by decoupling capacitors after current supply from the power management system stops.
+The shaded areas represent the ranges that system executes the application code.
+% Fig.~\ref{fig:execution_trace_one_cycle} shows the trace during one power cycle, and Fig.~\ref{fig:execution_trace_detailed} presents the first execution cycle in more detail.
 
-Three key observations that affect software designer's decision.
+Fig.~\ref{fig:execution_trace_detailed} presents the first execution cycle in detail. It shows several interesting differences between the traditional execution model and the actual operation.
+Among them, we highlight three key observations that affect software designer's decision.
 
 \begin{itemize}
-    \item \textbf{O1}: The capacitor voltage drops quickly to charge decoupling capacitor when system wakes-up ($t1$--$t2$).
-    \item \textbf{O2}: The system executes at sub-voltage using the decoupling capacitor, even after power supply stops ($t4$--$t5$).
+    \item \textbf{O1}: The capacitor voltage drops quickly to charge decoupling capacitor when the system wakes-up ($t1$--$t2$).
+    \item \textbf{O2}: The system executes at sub-voltage using the decoupling capacitors, even after power supply stops ($t4$--$t5$).
     \item \textbf{O3}: The decoupling capacitor discharges while the system is powered-off (after $t5$).
 \end{itemize}
 
+
 \begin{figure}
     \centering
     \includegraphics[width=\linewidth]{figs/cropped/detailed_execution_model.pdf}
@@ -76,15 +81,23 @@ Three key observations that affect software designer's decision.
     \label{fig:detailed_execution_model}
 \end{figure}
 
+% As we discuss in the following sections, all three observations significantly impact the performance of intermittent system designs.
+% We propose a detailed execution model which reflects these observations.
 Fig.~\ref{fig:detailed_execution_model} shows our detailed execution model, which reflects all the key observations.
+When the capacitor voltage reaches the power-on threshold, the voltage experience quick drop due to the buffering effects, instead of gradual reduction.
+After initialization, the system starts to execute at normal voltage (e.g., 3.3V).
+When the voltage hits the power-off threshold, the power supply stops but system now starts to execute using the buffered energy.
+Since voltage of capacitor decreases as it discharges, the system executes at sub-normal voltage until it reaches the voltage it cannot operate (e.g., 1.8V, typically known as Brown-Out Reset (BOR) voltage).
+Finally, until the next power-on, the remaining energy in decoupling capacitors continues to discharge.
 
-In the following sections, we discuss how this model benefits the software design.
+When designing intermittent systems with small capacitors, it is important for software designers to understand this model.
+In the following sections, we discuss the impact of this model to software design in more detail.
 
 \subsection{Impact on Power Efficiency}
 
-The traditional model implies that power consumed between power-on and power-off thresholds are entirely used for the computing system (including hardware initialization and recovery).
-However, our model reveals that huge energy is used for charging the decaps (\textbf{O1}) and discharged during power-off durations (\textbf{O3}).
-This implies that much smaller energy is used for the useful computation compared to the designer's expectation.
+The traditional model implies that power consumed between power-on and power-off thresholds are entirely used for the computing system.
+However, our model reveals that considerable energy is used for charging the decoupling capacitors (\textbf{O1}) and dissipated during power-off durations (\textbf{O3}).
+This implies that much smaller energy is used for the useful computation compared to the designer's expectation when using small capacitors.
 
 \begin{figure}
     \centering
@@ -93,15 +106,15 @@ This implies that much smaller energy is used for the useful computation compare
     \label{fig:power_distribution}
 \end{figure}
 
-Fig.~\ref{fig:power_distribution} shows the distribution of the energy consumed for each stage of intermittent execution within one power cycle, averaged over 50 executions, in various capacitor sizes. 
-The line represents the average time of useful computation.
+Fig.~\ref{fig:power_distribution} shows the distribution of the energy consumed for each stage of operation within one power cycle in various capacitor sizes, averaged over 50 executions. 
+The line in the secondary axis represents the average operation times for application code.
 The checkpoint is executed by the interrupt from the power management system, which is generated when the capacitor voltage reaches the power-off threshold (3.4V).
 Note that this is the last point for checkpoint execution according to the traditional model.
 
 The results shows that significant energy is wasted in decoupling capacitor.
-60.7\% of power is wasted in 470uF, 28.5\% in 1320uF case.
-The cost is more expensive when the capacitor size is small since the decaps discharge rate follows the RC-discharging circuits.
+The cost is more expensive when the capacitor size is small since the discharge rate follows the RC-discharging circuits.
 While using smaller capacitors shortens the power-off durations, the discharging behavior penalizes them most since RC-discharging circuits discharge exponential (in our case, 50\% of energy is discharged at the first 161 ms).
+As a result, 60.7\% of power is wasted in 470uF, and the rate decreases as the capacitor size increases, down to 28.5\% in 1320uF case.
 
 More importantly, this wasted energy is expected to be used for the computation in traditional execution model, as all the energy except for the initialization and checkpoint/recovery is expected to be used in computations.
 It brings significant errors between the two models in available energy for the execution.