Update on local

IEEE-conference-template-062824.tex

@@ -50,7 +50,7 @@ Intermittent Computing, Batteryless System.
 \input{sections/OurApproach.tex}
 \input{sections/RelatedWork.tex}
 \input{sections/Conclusion.tex}
-\input{sections/Notes.tex}
+% \input{sections/Notes.tex}
 
 \bibliographystyle{ieeetr}
 \bibliography{../refs}

sections/Conclusion.tex

@@ -1 +1,7 @@
-\section{Conclusion}
+\section{Conclusion}
+
+When designing software supports for intermittent systems, designers rely on an execution model that abstracts the hardware-level operations and describes the key behaviors of the system.
+However, the traditional model is failing to accurately model the actual behaviors as recent systems target smaller energy storages and more power-demanding architectures. 
+In this paper, we propose a new execution model, which incorporates the major source of this inconsistency: the buffering effects due to the system's inherent capacitance.
+Our model reveals that the traditional model can mislead the power efficiency of the system up to 5.62x and also may lead to unsafe checkpoint executions.
+Also, we propose several design guidelines, including methods to predict imminent power failure more accurately, which can improve the performance of existing checkpoint techniques up to 3.04x.

sections/Introduction.tex

@@ -12,9 +12,9 @@ In designing these state retention techniques, software designers rely on an \em
 
 Fig.~\ref{fig:introduction} illustrates such execution model commonly adopted in literature~\cite{ransfordMementos2011,jayakumarQUICKRECALL2014,maengAdaptive2020,dewinkelIntermittentlypowered2022,houTale2024,erataETAP2023,ghasemiPES2023,sanmiguelEH2018a}. 
 As energy accumulates, the voltage of the capacitor gradually increases.
-Once the voltage reaches the power-on threshold, the collected power is supplied to the system. 
-The system begins operation at this point, and execution is halted when the capacitor voltage reaches the power-off threshold. 
-Software designers aim to leverage this execution model to implement intermittent systems at minimal cost (e.g., executing checkpoints just before reaching the power-off threshold~\cite{jayakumarQUICKRECALL2014,maengSupporting2019,maengAdaptive2020,kortbeekBFree2020,netoDiCA2023}).
+Once the voltage reaches the power-on threshold $V_h$, the collected power is supplied to the system. 
+The system begins operation at this point, and execution is halted when the capacitor voltage reaches the power-off threshold $V_l$. 
+Software designers aim to leverage this execution model to implement intermittent systems at minimal cost (e.g., by executing checkpoints just before reaching the power-off threshold~\cite{jayakumarQUICKRECALL2014,maengSupporting2019,maengAdaptive2020,kortbeekBFree2020,netoDiCA2023}).
 
 \begin{figure}[t]
     \centering
@@ -31,13 +31,13 @@ As a result, recent studies have targeted operation times in the range of tens o
 % However, as energy storage size decreases, the traditional execution model no longer provides an accurate abstraction of actual execution behavior.
 However, as energy storage sizes decrease, the traditional execution model is failing to provide an accurate abstraction of actual execution behavior.
 % The challenge is that the traditional execution model does not provide precise abstraction of the real execution anymore when the energy storage is very small.
-The major source of this discrepancy is the buffering effect of the system's inherent capacitance, mostly coming from its decoupling capacitors.
+The major source of this discrepancy is the buffering effects of the system's inherent capacitance, mostly coming from its decoupling capacitors.
 This factor has been overlooked in the traditional model, as the inherent capacitance was considered negligible compared to the main energy storage.
 
 Decoupling capacitors are on-board capacitors that act as energy buffers.
 They are mandatory components since the buffered energy prevent transient voltage drop when the system suddenly draws a large current, such as during checkpointing (Sec.~\ref{sec:system_description}).
-However, at the same time, their buffering effect introduces discrepancies between the execution model and the actual system behavior.
-For example, during powers on, decoupling capacitors are rapidly charged using the energy in the storage, making capacitor voltage an unreliable estimate of available energy.
+However, at the same time, their buffering effects introduce discrepancies between the execution model and the actual system behavior.
+For example, during power-on, decoupling capacitors are rapidly charged using the energy in the storage, making capacitor voltage an unreliable estimate of available energy.
 This buffered energy also allows the system operate for a while at sub-normal voltages after the power supply is stopped.
 Additionally, between power cycles, decoupling capacitors discharge due to the resistance of the system, considerably lowering the power efficiency.
 In systems with smaller capacitors, these effects dominate the behaviors that are modeled in the traditional execution model.
@@ -61,4 +61,5 @@ In this paper, we propose a new execution model for intermittent systems which a
 In Sec.~\ref{sec:detailed_execution_model}, we demonstrate that understanding this model is critical for software designers:
 intermittent systems designed upon the traditional model can be up to 5.62x more energy-inefficient than expected and may fail to predict power-off timings accurately, leading to unsafe checkpointing. 
 In Sec.~\ref{sec:design_guidelines}, we propose design guidelines to implement efficient and safe intermittent systems with small energy storages, leveraging insights from our model.
-Our proposed power failure prediction methods improve end-to-end execution latencies by 3.04x in static and 2.86x in dynamic checkpointing schemes on average, without incurring additional overhead.
+Our guidelines include accurate power failure prediction methods that improve end-to-end execution latencies by 3.04x in static and 2.86x in dynamic checkpointing schemes on average, without incurring additional overhead.
+% Our power failure prediction methods improve end-to-end execution latencies by 3.04x in static and 2.86x in dynamic checkpointing schemes on average, without incurring additional overhead.

sections/OurApproach.tex

@@ -2,23 +2,25 @@
 \label{sec:design_guidelines}
 
 Based on the insights from our model, we propose design guidelines for efficient and safe intermittent systems.
-The effectiveness of the guidelines is evaluated on seven benchmarks on the reference system used in Sec.~\ref{sec:detailed_execution_model}. 
+The effectiveness of the guidelines is evaluated using seven benchmarks on the reference system used in Sec.~\ref{sec:detailed_execution_model}. 
 We ported five benchmarks from miBench~\cite{guthausMiBench2001} benchmark suite and implemented two computation kernels (\emph{matmul} and \emph{conv2d}) commonly used for evaluating intermittent systems in literature~\cite{kimLACT2024,maengSupporting2019,bhattacharyyaNvMR2022,ganesanWhat2019,akhunovEnabling2023}.
 
 We evaluate two popular existing checkpointing schemes: \emph{static} and \emph{dynamic}.
-The static scheme~\cite{} inserts checkpoint triggers at every loop latch in the program during compilation.
-At runtime, checkpoint triggers check the capacitor voltage and execute checkpoint only when it is below a predefined threshold.
-In contrast, the dynamic scheme~\cite{} does not modify the original program code.
-Instead, it executes checkpoints via interrupts from the power management system, generated when the power-off threshold is reached.
-All the evaluations are conducted with 470uF energy storage and 1mA of input current unless otherwise stated.
-
-\subsection{Delay Checkpoint Execution}
-
-Delaying checkpoint execution until the last possible moment is generally regarded as desirable in existing works~\cite{bhattiHarvOS2017}. 
-However, this has not been considered a critical property, since early checkpoint execution makes the system wake up sooner, incurring only a small cost of initialization and recovery. 
-For example, some static checkpoint approaches have explored proactive power-offs based on the program's worst-case execution time~\cite{choiCompilerDirected2022,reymondSCHEMATIC2024}, which can be overly pessimistic~\cite{raffeckWoCA2024}.
-On the other hand, Our model reveals that significant energy is wasted each time the system powers off (Sec.~\ref{sec:power_efficiency}).
-As a result, the importance of delaying checkpoint executions is greater than previously assumed.
+The static scheme~\cite{ransfordMementos2011,kimLivenessAware2023,kimLACT2024,maengAdaptive2018} inserts checkpoint triggers at every loop latch in the program during compilation.
+At runtime, checkpoint triggers examine $V_{ES}$ and execute checkpoint only when it is below a predefined threshold.
+In contrast, the dynamic scheme~\cite{jayakumarQUICKRECALL2014,maengSupporting2019,balsamoHibernus2016,balsamoHibernus2015,kortbeekTimesensitive2020} does not modify the original program code.
+Instead, it executes checkpoints via interrupts from the power management system, generated when $V_{ES}$ reaches $V_l$.
+All the evaluations are conducted with 470uF energy storage and 1mA of input current at 1.9V, unless otherwise stated.
+
+\subsection{Delay Checkpoint Executions}
+\label{sec:delay_checkpoint_execution}
+
+The first design practice we propose is to delay checkpoint executions until the last possible moment.
+While this practice is generally regarded as desirable in existing works~\cite{ransfordMementos2011,bhattiHarvOS2017}, it has not been recognized as a critical property.
+Under the traditional execution model, early checkpoint execution is often considered acceptable as it allows the system to wake up sooner, incurring only minor costs for initialization and recovery.
+For example, some approaches have explored proactive power-offs based on the program's worst-case execution time~\cite{choiCompilerDirected2022,reymondSCHEMATIC2024}, which can be overly pessimistic~\cite{raffeckWoCA2024}.
+On the other hand, our model reveals that significant energy is wasted each time the system powers off (Sec.~\ref{sec:power_efficiency}), highlighting the impact of delaying checkpoint executions.
+% As a result, the importance of delaying checkpoint executions is greater than previously assumed.
 
 \begin{figure}
     \centering
@@ -27,31 +29,36 @@ As a result, the importance of delaying checkpoint executions is greater than pr
     \label{fig:expr_checkpoint_voltages}
 \end{figure}
 
-Fig.~\ref{fig:expr_checkpoint_voltages} shows the benchmark execution times in dynamic checkpoint scheme, across various checkpoint execution voltages.
-A 1100uF capacitor is used and the execution times are normalized to the 3.4V case. 
-The figure shows that executing checkpoint earlier is considerably inefficient: 1.38x and 2.45x with 3.7V and 4.0V configurations, respectively.
-Consequently, it is important to execute as long as possible whenever the system wakes up.
-In the next section, we discuss how this can be implemented in the existing intermittent systems.
-
-\subsection{Use Vdd and Known Voltage for Checkpoint Execution}
-\label{sec:use_vdd}
-
-Sec.~\ref{sec:predicting_power_failures} demonstrates that capacitor voltage is not a good estimate for the system's remaining execution time.
-Instead, we propose using Vdd to accurately estimate the imminent power-off, as in works that do not have the power management systems (Sec.~\ref{sec:related_work}).
-Also, when dealing with the Vdd, it is important to consider the operations of ADC in sub-normal voltage (Sec.~\ref{sec:sub_normal_execution}).
-For consistent operation of ADCs, the computing system needs a voltage source with a known value.
-In STM32L5 and MSP430, there exist internal reference voltage source of 1.2V; an external voltage reference~ (e.g., TI LVM431~\cite{texasinstrumentsLMV431}) can be considered otherwise.
-% Note that the reference voltage should be lower than the minimal operating voltage of MCU as it is regulated from Vdd.
-We propose two efficient implementations, each for dynamic and static checkpoint schemes.
-
-$T_{sta}$ is a setup for static checkpoint techniques, which poll the capacitor voltage and execute checkpoint only the voltage is below a threshold.
-Instead of reding the energy storage voltage, $T_{sta}$ reads the known voltage $V_{ref}$, which results in the same value of $\lfloor V_{ref}/V_{dd} \cdot 2^n \rfloor$ when operating on normal voltage.
-During sub-voltage execution, this value increases as $V_{dd}$ decreases.
-Given that the target threshold voltage for checkpoint execution is $V_{th}$, software designers can compare the ADC value with $\lfloor V_{ref}/V_{th} \cdot 2^n \rfloor$ to determine whether to execute checkpoint.
+Fig.~\ref{fig:expr_checkpoint_voltages} presents the benchmark execution times in dynamic checkpoint scheme, across various checkpoint execution voltages.
+A 1100 uF capacitor is used as an energy storage and the execution times are normalized to the 3.4V case. 
+The results show that executing checkpoints earlier is significantly inefficient: by 1.38x and 2.45x in 3.7V and 4.0V configurations, respectively.
+Moreover, the overhead is consistent across all benchmarks since early checkpoint executions directly reduce the energy available for the computing system.
+Consequently, delaying checkpoint executions is crucial when designing state-retention techniques.
+Achieving this fundamentally depends on accurately predicting imminent power failures, which is the focus of the next section.
+% Consequently, it is important to execute as long as possible whenever the system wakes up.
+% In the next section, we discuss how this can be implemented in the existing intermittent systems.
+
+\subsection{Use $V_{dd}$ with a Reference Voltage for Checkpoint Signals}
+\label{sec:use_vdd_for_checkpoint}
+
+Sec.~\ref{sec:predicting_power_failures} demonstrates that $V_{ES}$ is not a good estimate for the system's remaining execution time.
+Instead, we propose using $V_{dd}$ to more accurately estimate the imminent power-off events, similar to approaches used in systems without power management system (Sec.~\ref{sec:related_work}).
+Also, when obtaining $V_{dd}$, it is important to account for the operations of ADC in sub-normal voltage conditions (Sec.~\ref{sec:sub_normal_execution}).
+
+For consistent operation of ADCs, we adopt a voltage source with a known value of $V_{ref}$.
+In STM32L5 and MSP430, an internal reference voltage source of 1.2V is available; alternatively, an external voltage reference (e.g., TI LVM431~\cite{texasinstrumentsLMV431}) can be used.
+Note that $V_{ref}$ should be lower than the minimal operating voltage of MCU (e.g., 1.7V) as $V_{ref}$ is generated by regulating $V_{dd}$.
+We propose two efficient implementations, $T_{sta}$ and $T_{dyn}$, to accurately detect the imminent power-off events in static and dynamic checkpoint schemes.
+
+$T_{sta}$ is designed for static checkpoint techniques.
+Instead of reading $V_{ES}$ at checkpoint triggers, $T_{sta}$ reads $V_{ref}$. 
+This results in the same value of $\lfloor V_{ref}/V_{dd} \cdot 2^n \rfloor$ when operating on normal voltage, where $n$ is the ADC resolution.
+During sub-voltage execution, this value increases as $V_{dd}$ decreases, as discussed in Sec.~\ref{sec:sub_normal_execution}.
+Given that the target threshold voltage for checkpoint execution is $V_{th}$, software designers can compare the ADC value against $\lfloor V_{ref}/V_{th} \cdot 2^n \rfloor$ to determine whether to execute a checkpoint.
 
 On the other hand, $T_{dyn}$ utilizes an on-chip comparator, which is available in most modern MCUs including STM32L5 and MSP430.
-As $V_{ref}$ is always lower than $V_{dd}$, we use a voltage divider using two resistors, $R1$ and $R2$, to reduce $V_{dd}$ and compare it with $V_{ref}$.
-Specifically, we set $R1$ and $R2$ to satisfy $\frac{R2}{R1+R2} \cdot V_{th} = V_{ref}$ so that the comparator generates an interrupt when $V_{dd}$ reaches the threshold voltage $V_{th}$.
+As $V_{ref}$ is always lower than $V_{dd}$, we use a voltage divider consisting of two resistors, $R1$ and $R2$, to scale $V_{dd}$ and compare it with $V_{ref}$.
+Specifically, we configure $R1$ and $R2$ to satisfy $\frac{R2}{R1+R2} \cdot V_{th} = V_{ref}$, so the comparator generates an interrupt when $V_{dd}$ reaches the threshold voltage $V_{th}$.
 
 % T2 is setup for static checkpoint techniques, which poll the capacitor voltage to determine whether execute checkpoint or not.
 % Instead of reading the capacitor voltage, it reads the reference voltage.
@@ -79,7 +86,15 @@ Specifically, we set $R1$ and $R2$ to satisfy $\frac{R2}{R1+R2} \cdot V_{th} = V
     \label{fig:expr_precise_checkpoint_timings}
 \end{figure}
 
-Fig.~\ref{fig:expr_precise_checkpoint_timings} shows 
+Fig.~\ref{fig:expr_precise_checkpoint_timings} shows the average end-to-end execution times of the benchmarks over 30 iterations, comparing the traditional systems with the proposed setups.
+Fig.~\ref{fig:expr_precise_checkpoint_timings_static} illustrates the performance of $T_{sta}$ and Fig.~\ref{fig:expr_precise_checkpoint_timings_dynamic} presents the result for $T_{dyn}$.
+The error bars indicate the minimum and maximum measured execution times for each benchmark.
+The results clearly demonstrate that the execution time is significantly improved in both systems by extending the operation at sub-normal voltages: 3.04x in $T_{sta}$ and 2.85x in $T_{dyn}$.
+Furthermore, these improvements are consistent across all benchmarks, regardless of the application characteristics, highlighting the general effectiveness of the proposed setups.
+
+Another advantage of the proposed setups is their simplicity and practical applicability.
+Since the both setups only modify the method to detect imminent power failures and leave the checkpoint algorithms unchanged, it is straightforward to apply them in existing checkpoint techniques.
+Furthermore, the proposed setups can reduce the complexity of the system, as they eliminate the need for communication (e.g., interrupt or access to $V_{ES}$) between the energy storage system and the computing system.
 
 \subsection{Checkpoint Techniques and Evaluation Methods}
 % \subsection{Design Checkpoint Techniques for Sufficient Power Duration}

sections/OurModel.tex

@@ -3,11 +3,11 @@
 
 In this section, we describe our execution model and its implications for software design.
 Sec.~\ref{sec:system_description} introduces the target architecture and the reference system used for evaluations.
-In Sec.~\ref{sec:execution_model}, we present the proposed execution model, derived from key observations obtained through experimental results.
-In the following three sections, we discuss how this model affects both the power efficiency and correctness of software design.
-Finally, in Sec.~\ref{sec:other_architectures}, we evaluate the effectiveness of our model across systems with different architectural configurations. 
+Sec.~\ref{sec:execution_model} presents our execution model, derived from key observations obtained through experimental results.
+In the subsequent three sections, we discuss how this model affects both the power efficiency and correctness of software design.
+Finally, in Sec.~\ref{sec:other_architectures}, we evaluate the effectiveness of our model across systems with various architectural configurations. 
 
-\subsection{System Description}
+\subsection{Target Architecture and Reference System}
 \label{sec:system_description}
 
 \begin{figure}
@@ -18,7 +18,7 @@ Finally, in Sec.~\ref{sec:other_architectures}, we evaluate the effectiveness of
 \end{figure}
 
 A typical intermittent system consists of two main components: a power management system and a computing system, as illustrated in Fig.~\ref{fig:hardware_setup}.
-The power management system is responsible for accumulating the incoming energy into storage and providing a stable-voltage current to the computing system.
+The power management system is responsible for accumulating the incoming energy into storage ($C_{ES}$) and providing a stable-voltage current to the computing system.
 The computing system equips NVMs along with the MCU and peripherals, and utilize the NVMs for state retention between power failures.
 
 This setup includes two notable decoupling capacitors that affect the execution model of intermittent systems.
@@ -27,9 +27,11 @@ The second capacitor (C2) is part of the computing system and is used for stabil
 
 Recent studies have increasingly explored 32-bit architectures for computing systems~\cite{shihIntermittent2024,wuIntOS2024,kimRapid2024,akhunovEnabling2023,kimLACT2024,kimLivenessAware2023,parkEnergyHarvestingAware2023,kortbeekWARio2022,khanDaCapo2023,barjamiIntermittent2024,songTaDA2024}, as emerging applications on intermittent systems, such as Deep Neural Networks (DNNs)~\cite{houTale2024,yenKeep2023,khanDaCapo2023,gobieskiIntelligence2019,islamEnabling2022,kangMore2022,leeNeuro2019,islamZygarde2020,custodeFastInf2024,barjamiIntermittent2024,songTaDA2024}, demand greater computational capabilities~\cite{bakarProtean2023a,carontiFinegrained2023}.
 In this context, we employ a custom-built board featuring a 32-bit ARM Cortex-M33 processor (STM32L5, operating at 16Mhz) with 512KB of Ferroelectric RAM (FRAM) as our reference system.
-For the power management system, we use a TI BQ25570-based board with power-on and power-off thresholds of 4.9 V and 3.4 V, respectively.
+For the power management system, we use a TI BQ25570-based board with configuration of $V_h$ = 4.9V and $V_l$ = 3.4V.
+% For the power management system, we use a TI BQ25570-based board with power-on and power-off thresholds of 4.9 V and 3.4 V, respectively.
 % A TI BQ25570 based board is used for the power management system, with power-on and off thresholds of 4.9V and 3.4V, respectively.
-We empirically select 22uF and 220uF capacitors for C1 and C2, respectively, as these are the minimum capacitor sizes for stable checkpoint and recovery.
+We empirically select 22uF and 220uF capacitors for C1 and C2, respectively, as the capacitors smaller then these cannot provide a reliable voltage for stable checkpoint and recovery.
+% We empirically select 22uF and 220uF capacitors for C1 and C2, respectively, as these are the minimum capacitor sizes for stable checkpoint and recovery.
 Sec.~\ref{sec:other_architectures} evaluates the generality of our model across different architectures, such as systems with Magnetic RAM (MRAM) and a 16-bit core (e.g., MSP430).
 
 % In this work, our goal is to model the buffering effects of these capacitors and evaluate their implications on software designs.
@@ -59,18 +61,19 @@ Sec.~\ref{sec:other_architectures} evaluates the generality of our model across
 \end{figure}
 
 To derive general execution model with the effects of decoupling capacitors, we first present a sample measurement from our reference system.
-To achieve an operation time of 50ms under 1.5mA current supply, we use a 470uF capacitor for energy storage.
-Fig.~\ref{fig:execution_trace_one_cycle} illustrates the voltage traces of the energy storage and the MCU operating voltage (Vdd) over a single power cycle.
-Note that Vdd is maintained by decoupling capacitors after current supply from the power management system stops.
+Within this paper, we denote the voltage of the energy storage $C_{ES}$ as $V_{ES}$ and the MCU operating voltage as $V_{dd}$.
+To achieve an operation time of 50ms under 1.5mA current supply, we use a 470uF capacitor for $C_{ES}$.
+Fig.~\ref{fig:execution_trace_one_cycle} illustrates the voltage traces of $V_{ES}$ and $V_{dd}$ over a single power cycle.
+Note that $V_{dd}$ is maintained by decoupling capacitors after current supply from the power management system stops.
 The shaded areas represent the periods that system executes the application code.
 % Fig.~\ref{fig:execution_trace_one_cycle} shows the trace during one power cycle, and Fig.~\ref{fig:execution_trace_detailed} presents the first execution cycle in more detail.
 
-Fig.~\ref{fig:execution_trace_detailed} presents the first execution cycle in more detail. It shows several interesting differences between the traditional execution model and the actual operation.
+Fig.~\ref{fig:execution_trace_detailed} presents the first execution cycle in more detail. It reveals several differences between the traditional execution model and the actual operation.
 Among them, we highlight three key observations that affect software design decisions.
 
 \begin{itemize}
-    \item \textbf{O1}: The capacitor voltage drops rapidly to charge decoupling capacitor when the system wakes up ($t1$--$t2$).
-    \item \textbf{O2}: The system operates at sub-voltage using the decoupling capacitors, even after power supply stops ($t4$--$t5$).
+    \item \textbf{O1}: The capacitor voltage ($V_{ES}$) drops rapidly to charge decoupling capacitors when the system wakes up ($t1$--$t2$).
+    \item \textbf{O2}: System operates at sub-normal voltage using decoupling capacitors, even after power supply stops ($t4$--$t5$).
     \item \textbf{O3}: Decoupling capacitors discharge while the system is powered off (after $t5$, as shown in Fig.~\ref{fig:execution_trace_one_cycle}).
 \end{itemize}
 
@@ -84,10 +87,10 @@ Among them, we highlight three key observations that affect software design deci
 % As we discuss in the following sections, all three observations significantly impact the performance of intermittent system designs.
 % We propose a detailed execution model which reflects these observations.
 Fig.~\ref{fig:detailed_execution_model} illustrates our detailed execution model, incorporating these key observations.
-When the capacitor voltage reaches the power-on threshold, the voltage experience a rapid drop due to the buffering effects (\circled{1}), instead of gradual decline.
+When $V_{ES}$ reaches $V_h$, the voltage experience a rapid drop due to the buffering effects (\circled{1}), instead of gradual decline.
 After initialization (\circled{2}), the system begins execution at normal operating voltage (\circled{3}), 3.3V for example.
-When the voltage hits the power-off threshold, the power supply stops but system now starts to operate using the buffered energy (\circled{4}).
-Since the voltage of the decoupling capacitor decreases as it discharges, the system executes at sub-normal voltage until it reaches the voltage it cannot operate (e.g., 2.5V).
+When the voltage hits $V_l$, the power supply stops but system now starts to operate using the buffered energy (\circled{4}).
+Since the voltage of the decoupling capacitors decreases as they discharge, the system executes at sub-normal voltage until it reaches the voltage level it cannot operate (e.g., 2.5V in Fig.~\ref{fig:execution_trace}).
 % This voltage is known as Brown-Out Reset (BOR) voltage and is typically in a range of 1.7V to 2.5V in modern MCUs~\cite{}.
 Finally, until the next power-on event, the remaining energy in decoupling capacitors continues to discharge (\circled{5}).
 
@@ -97,7 +100,7 @@ In the following sections, we discuss the impact of our model to software design
 \subsection{Impact on Power Efficiency}
 \label{sec:power_efficiency}
 
-The traditional model implies that the energy consumed between power-on and power-off thresholds are entirely used in the computing system.
+The traditional model implies that the energy consumed between $V_h$ and $V_l$ is entirely used in the computing system.
 However, our model reveals that considerable energy is used for charging the decoupling capacitors (\textbf{O1}) and dissipated during power-off durations (\textbf{O3}).
 This indicates that much smaller energy may be used for the useful computation compared to the designer's expectation.
 
@@ -109,16 +112,17 @@ This indicates that much smaller energy may be used for the useful computation c
 \end{figure}
 
 Fig.~\ref{fig:power_distribution} shows the distribution of the energy consumption for each stage of operation within one power cycle, averaged over 50 executions, where 1mA of input current is provided at 1.9V.
-The x-axis represents capacitor sizes and the line in the secondary axis represents the average operation times for application code.
-The checkpoint is executed by the interrupt from the power management system~\cite{}, which is generated when the capacitor voltage reaches the power-off threshold (3.4V).
-Note that this is the most efficient point for checkpoint execution according to the traditional model.
+The x-axis represents energy storage sizes and the line in the secondary axis represents the average operation times for application code.
+The checkpoint is executed by the interrupt from the power management system~\cite{jayakumarQUICKRECALL2014,maengSupporting2019,balsamoHibernus2016,balsamoHibernus2015,kortbeekTimesensitive2020}, which is generated when $V_{ES}$ reaches $V_l$ (3.4V).
+Note that this is the most efficient point for checkpoint execution according to the traditional model (i.e., just before the poweroff).
 
 The results shows that significant energy is wasted in the decoupling capacitors.
-For example, 60.7\% of power is wasted during the power-off duration (denoted as \emph{Dischrged}) in 470uF case.
-The discharging behavior can be modeled as an RC-discharging circuit (i.e., $q=CVe^{-\frac{1}{RC}t}$), which exhibits an exponential discharge rate.
-As a result, the energy loss due to discharging is more expensive when the capacitor size is small.
-In our case, 50\% of energy is discharged within the first 161 ms.
-While the discharge rate decreases with larger capacitor sizes, it remains significant;
+For example, 60.7\% of power is wasted during the power-off duration (denoted as \emph{Dischrged}) in 470uF case, leaving just 13.1\% of the energy for computation.
+The discharging behavior can be modeled as an RC-discharging circuit (i.e., $q=CVe^{-\frac{t}{RC}}$), which exhibits an exponential discharge rate.
+Indeed, we observe that 50\% of energy is discharged within the first 161 ms.
+Since recharging $C_{ES}$ takes xx secs even in 470uF configuration, most of the buffered energy is lost at the next power-on regardless of the capacitor sizes.
+As a result, the energy loss ratio due to discharging is larger when the capacitor size is small.
+While this ratio decreases with larger $C_{ES}$, it remains significant;
 for example, in the 1320uF case, 28.5\% of energy is discharged, which is still non-negligible.
 % The discharge rate decreases as the capacitor size increases, down to 28.5\% in 1320uF case, which is still not negligible.
 % The cost is more expensive when the capacitor size is small since the discharge rate follows the RC-discharging circuits.
@@ -127,11 +131,11 @@ for example, in the 1320uF case, 28.5\% of energy is discharged, which is still
 
 Another important observation is the error introduced by the traditional model.
 The traditional model expects both the energies, \emph{Execution} and \emph{Discharged}, are used for computation.
-This introduces significant errors, up to 5.62x in 470uF setup.
+This introduces huge errors, up to 5.62x in 470uF setup, for example.
 In the same context, the traditional model predicts that using a 470uF capacitor instead of a 1320uF would result in only 1.22x overhead in energy efficiency, while the actual difference is 4.71x.
 % However, our model shows that the actual energy efficiency differs by xx\% in reality, brining xx\% error in the traditional model.
 This can significantly mislead system designers when they select capacitor sizes by considering tradeoffs between overall efficiency and reactiveness.
-In Sec.~\ref{sec:design_guidelines}, we explore strategies to minimize overhead caused by discharging when designing software techniques.
+In Sec.~\ref{sec:design_guidelines}, we explore strategies to minimize the inefficiencies caused by discharging when designing software techniques.
 
 % More importantly, this wasted energy is expected to be used for the computation in traditional execution model, as all the energy except for the initialization and checkpoint/recovery is expected to be used in computations.
 % It brings significant errors between the two models in available energy for the execution.
@@ -144,13 +148,14 @@ In Sec.~\ref{sec:design_guidelines}, we explore strategies to minimize overhead
 \subsection{Impact on Predicting Power Failures}
 \label{sec:predicting_power_failures}
 
-According to the traditional model, system states should be saved to NVM before reaching power-off threshold, as the system halts at this point.
+According to the traditional model, system states should be saved to NVM before $V_{ES}$ reaches $V_l$, as the system halts at this point.
 On the other hand, our model shows that the system may continue operating using the energy stored in the decoupling capacitors (\textbf{O2}). 
 Since modern MCUs can operate across a wide range of supply voltages (e.g., from 1.7V to 3.6V in STM32L5 and MSP430), the computing system is executed until the voltage of decoupling capacitors drops to the minimum operating level.
 % Modern MCUs can operate on a range of supply voltages (e.g., from 1.7V to 3.6V for STM32L5 and MSP430).
 % Since the voltage of decoupling capacitors decreases as the discharge, the computing system is executed until the voltage reaches the minimum operating voltage.
 % While the voltage of decoupling capacitors decreases as they discharge, the computing system operates since modern MCUs can operate on a range of supply voltages (e.g., from 1.7V to 3.6V for STM32L5 and MSP430).
-This makes the energy storage voltage not a reliable estimate of the remaining execution time.
+This makes $V_{ES}$ not a reliable indicator for the imminent power-off.
+% This makes the $V_{ES}$energy storage voltage not a reliable estimate of the remaining execution time.
 
 \begin{figure}
     \centering
@@ -171,33 +176,34 @@ This makes the energy storage voltage not a reliable estimate of the remaining e
 
 % Modern MCUs can operate on wide range of operating voltages (e.g., from 1.7V to 3.6V for STM32L5 and MSP430).
 
-Fig.~\ref{fig:sub_voltage_execution} presents the ratio of the times executed under sub-voltage to the total execution times, averaged over 30 measurements.
+Fig.~\ref{fig:sub_voltage_execution} presents the ratio of the times executed under sub-normal voltage to the total execution times, averaged over 30 measurements.
 The x-axis represents different capacitor sizes and the colors indicate the voltage levels at which the system stops operation.
-We evaluate a range of stop voltages from 1.7V to 2.5V since not all components in the computing system may function at the lowest voltage (Sec.~\ref{sec:sub_normal_execution}).
+We evaluate a range of stop voltages from 1.7V to 2.5V since not all components in the computing system may function at the lowest voltage level (Sec.~\ref{sec:sub_normal_execution}).
 Also, we examine two cases with different input currents of 1mA (Fig.~\ref{fig:sub_voltage_execution_1mA}) and 3mA (Fig.~\ref{fig:sub_voltage_execution_3mA}), to assess the impact of varying input power.
 
 The figure shows that a significant portion of MCU operation occurs at sub-normal voltage.
 For example, when 470uF capacitor is used at 1mA input current (Fig.~\ref{fig:sub_voltage_execution_1mA}), 82.8\% of computation takes place \emph{after} the power-off threshold.
-This ratio decreases as the system powers off earlier (reducing sub-voltage operation time) or the input current increases (extending operation time at normal voltage).
-Under 1000uF is the major focus of this paper.
+This ratio decreases as the system stops earlier (reducing sub-voltage operation time) or the input current increases (extending operation time at normal voltage).
+However, at least 13.0\% of computations are operated in sub-normal voltage even in a highly optimistic configurations (1320uF in Fig.~\ref{fig:sub_voltage_execution_3mA}).
+% Overall, the average sub-voltage operation ratio is xx\% for the configurations exhibiting less than 100 ms, which is the main focus of this paper. 
 
-These values can be directly translated to the inefficiencies of the system based on the traditional model.
-For example, in the case of 470uF with 1mA input current, systems executing checkpoint at power-off threshold may operate 16.3ms.
+These values can be directly translated to the inefficiencies of the systems based on the traditional model.
+For example, in the case of 470uF with 1mA input current, systems executing checkpoint at $V_l$ may operate 16.3ms.
 However, the system could operate for an additional 29.4ms if the checkpoint is executed at 2.5V.
 At the next power-on, the decoupling capacitors discharge to similar voltage levels in both cases, as their discharge behavior follows an exponential curve (Sec.~\ref{sec:power_efficiency}).
 As a result, failing to utilize the available energy at sub-normal voltage introduces significant power efficiency overhead.
 % Although early checkpoint execution may save some energy in decoupling capacitors, the saved energy is not preserved as discussed in Sec.~\ref{sec:power_efficiency}.
-In Sec.~\ref{sec:design_guidelines}, we validate this aspect and propose methods to predict the power-off time more accurately.
+In Sec.~\ref{sec:use_vdd_for_checkpoint}, we validate this aspect and propose methods to fully utilize the buffered energy.
 
 \subsection{Impact of Sub-normal Voltage Execution}
 \label{sec:sub_normal_execution}
 
 The traditional model leads the software designers to assume that the system is executed under a stable voltage.
-However, a significant portion of execution may happen after the power-off threshold at sub-normal voltage (\textbf{O3}), as discussed in Sec.~\ref{sec:predicting_power_failures}.
-Being aware of this is crucial to software designers since the peripherals and analog components may function differently at sub-normal voltage.
+However, a significant portion of execution may happen after the power-off threshold at sub-normal voltages (\textbf{O3}), as discussed in Sec.~\ref{sec:predicting_power_failures}.
+Being aware of this is crucial to software designers since analog components and peripherals may function differently at sub-normal voltage.
 
 Two of the most relevant examples are Analog-Digital Converters (ADCs) and external NVMs.
-They play an important role in checkpointing, since ADCs are often used to estimate power-off time by reading the capacitor voltage and NVM serves as the storage for checkpoints.
+They play an important role in checkpointing, since ADCs are often used to determine checkpoint execution by reading $V_{ES}$ and NVM serves as the storage for checkpoints.
 At the same time, they are likely to operate at sub-normal voltages, as it is most efficient to execute checkpoint just before power-off.
 % Incorrect execution of these components may lead to unsafe or incomplete checkpoint executions.
 
@@ -219,17 +225,18 @@ At the same time, they are likely to operate at sub-normal voltages, as it is mo
 \end{figure}
 
 Fig.~\ref{fig:adc_error} shows the behavior of ADCs in sub-normal voltage.
-ADC quantizes the input analog voltage into the range of discrete $2^n$ values from 0 to $V_{ref}$, where $n$ is a resolution and $V_{ref}$ is a reference voltage, and cannot read the input voltage larger than $V_{ref}$.  
-As STM32L5 is designed to use Vdd as reference voltage, accessing the ADC during sub-normal voltage operation leads to inconsistent results.
-As shown in the figure, the ADC returns values higher than the measurements since ADC representation range is decreased as Vdd drops.
-As a result, during sub-normal voltage operation, the system may incorrectly interpret ADC results as there is sufficient energy and decide not to execute a checkpoint.
+ADC quantizes the input analog voltage into the range of discrete $2^n$ values from 0 to the given reference voltage, where $n$ is a resolution.
+Since $n$ is fixed, using smaller reference voltage results in higher resolution, at the cost of reduced representation range.
+As STM32L5 is designed to use $V_{dd}$ as a reference voltage, accessing the ADC during sub-normal voltage operation leads to inconsistent results.
+As shown in the figure, the ADC returns values higher than the measurements since its representation range is decreased as $V_{dd}$ drops.
+As a result, during sub-normal voltage operation, the system may incorrectly interpret ADC results as if there is sufficient energy in $C_{ES}$ and decide not to execute a checkpoint, resulting in loss of the progress during the entire power cycle.
 
-Also, intermittent systems typically designed with the use of peripherals, including sensors~\cite{yildizAdaptable2024,dangIoTree2022,afanasovBatteryless2020,maengAdaptive2020}, wireless communication modules~\cite{katanbafMultiScatter2021,dewinkelIntermittentlypowered2022,babatundeGreentooth2024} or external NVMs~\cite{dewinkelIntermittentlypowered2022,kimLACT2024,kimLivenessAware2023,akhunovEnabling2023}, which have their own minimum operating voltage requirements.
+Also, intermittent systems typically designed to be deployed with peripherals, including sensors~\cite{yildizAdaptable2024,dangIoTree2022,afanasovBatteryless2020,maengAdaptive2020}, wireless communication modules~\cite{katanbafMultiScatter2021,dewinkelIntermittentlypowered2022,babatundeGreentooth2024} or external NVMs~\cite{dewinkelIntermittentlypowered2022,kimLACT2024,kimLivenessAware2023,akhunovEnabling2023}, which have their own minimum operating voltage requirements.
 % Also, some peripherals may not work below certain voltage.
 Fig.~\ref{fig:fram_drror} illustrates the error rate of FRAM in the reference system at different voltages, showing FRAM cannot operate reliably below 2.4V.
 Since the system continues operating until it reaches the lowest MCU operation voltage (e.g., 1.7V), software designers must ensure that peripherals are accessed only at safe voltage levels.
-Failing to this can result in corrupted data or incomplete checkpointing.
-In Sec.~\ref{sec:design_guidelines}, we propose two techniques that can safely estimate the power-off time under sub-normal voltage conditions.
+Failing to this can result in corrupted sensor data or unsafe checkpointing.
+% In Sec.~\ref{sec:design_guidelines}, we propose two techniques that can safely estimate the power-off time under sub-normal voltage conditions.
 
 \subsection{Sensitivity to Architectural Designs}
 \label{sec:other_architectures}
@@ -255,11 +262,11 @@ In Sec.~\ref{sec:design_guidelines}, we propose two techniques that can safely e
     }
     \end{table}
 
-To verify generality of our model, we evaluate it using two additional architectural setups.
+To assess generality, we evaluate the proposed model across two additional architectural setups.
 Table~\ref{tab:architectures} shows the detailed parameters of the target architectures.
 A1 shares the same configuration as the reference system but equips MRAM (Everspin MR5A16ACYS35) instead of FRAM.
 This setup is included since MRAM is also gaining attention as a next generation NVM~\cite{akhunovEnabling2023,bakarProtean2023a,dewinkelIntermittentlypowered2022,wuIntOS2024}.
-Second target is the MSP430, which has been the mostly adopted 16-bit platform in intermittent system research.
+Second target is MSP430, which has been the mostly adopted 16-bit platform in intermittent system research.
 For both systems, the architectural parameters are set to achieve an operation time of approximately 50 ms.
 
 \begin{figure}
@@ -271,12 +278,12 @@ For both systems, the architectural parameters are set to achieve an operation t
 
 Fig.~\ref{fig:other_architectures} shows the results for different power-off voltages.
 The bars on the left illustrate the energy breakdown in a single power cycle, and the bars on the right represent the ratio of the execution time operated at sub-voltage.
-The most noticeable difference is ratio of energy consumed during the ramp-up and init stage.
+The most noticeable difference is ratio of energy consumed during the \emph{Ramp-up \& Init} stage.
 While A1 consumes 63.4\% power at this stage on average, only 5.6\% of energy is consumed in A2.
-This is because A1 is configured to use external MRAM, which exhibits significantly higher leakage current than FRAM used in the reference system.
-In contrast, MSP430 (A2) is equipped with on-chip FRAM, which has much lower leakage.
+This is because A1 is configured with an external MRAM, which exhibits significantly higher leakage current even compared to the FRAM used in the reference system.
+In contrast, A2 is equipped with on-chip FRAM, which has much lower leakage.
 
 Despite these differences, both architectures exhibit high sub-voltage execution rates, up to 55.5\% in A1 and 70.1\% in A2.
-In addition, discharged energy takes considerable portion in both A1 (31.4\%) and A2 (52.0\%) at 3.3V power-off voltage configuration, which represents the techniques based on the traditional model that halt immediately at power-off threshold.
+In addition, discharged energy takes considerable portion in both A1 (31.4\%) and A2 (52.0\%) at 3.3V power-off voltage configuration, which represents the techniques based on the traditional model that halt immediately at $V_{ES}$.
 In summary, the evaluation demonstrates that the modeled buffering effects are general and their impacts are significant across different system architectures.
 % In summary, the evaluation reveals that the buffering effect of system's capacitance and its implications are general in other systems.

sections/RelatedWork.tex

@@ -1,14 +1,15 @@
 \section{Related Work}
 \label{sec:related_work}
 
-This work can be compared to the existing modeling-based approaches that estimate the latency or efficiency of the intermittent systems~\cite{kimRapid2024,houTale2024,erataETAP2023,ghasemiPES2023,sanmiguelEH2018a,sanmiguelEH2018}.
-The primary focus of these works is to find the most efficient design configurations (e.g., capacitor size, input power or checkpoint techniques~\cite{kimRapid2024}) for the given application.
-Zhan et al.~\cite{zhanExploring2022} especially focused on the tradeoff of capacitor size and the forward progress.
-However, the modelings in these works assume the entire energy discharged in the capacitor is used in the computing systems, overlooking the buffering effects that are addressed in this work.
-Furthermore, this work propose several practical guidelines that can improve the efficiency of the existing techniques with minimal efforts.
+This work can be compared to existing modeling-based approaches that estimate the timing or efficiency of intermittent systems~\cite{kimRapid2024,houTale2024,erataETAP2023,ghasemiPES2023,sanmiguelEH2018a,sanmiguelEH2018}.
+The primary focus of these works is to identify the most efficient design configurations (e.g., capacitor size, input power or checkpoint techniques~\cite{kimRapid2024}) for a given application.
+Zhan et al.~\cite{zhanExploring2022} especially examined the trade-offs between capacitor sizes and forward progress.
+However, the modelings in these works assume that the entire energy discharged from the capacitor is utilized by computing system, overlooking the buffering effects addressed in this work.
+Furthermore, our work proposes several practical guidelines to improve the efficiency of existing techniques with minimal efforts.
 
-In some works that do not have a dedicated power management system and directly supply unregulated power to the computing system~\cite{balsamoHibernus2015,balsamoHibernus2016,netoDiCA2023,raffeckCO2CoDe2024,reymondEarlyBird2024}, the MCU operating voltage (Vdd) has been used for checkpoint signals.
-This is natural in these works since the voltage of the energy storage is always same as Vdd and the MCU operates in varying voltage levels.
-On the other hand, our work demonstrates that considering sub-normal voltage operation is also important in the systems with a regulated power supply, which is the majority.
+In some works that do not have a dedicated power management system and directly supply unregulated power to the computing system~\cite{balsamoHibernus2015,balsamoHibernus2016,netoDiCA2023,raffeckCO2CoDe2024,reymondEarlyBird2024}, the MCU operating voltage ($V_{dd}$) has been used as a checkpoint signal.
+This is natural in these works since the voltage of the energy storage ($V_{ES}$) is always identical to $V_{dd}$.
+% This is natural in these works since the voltage of the energy storage is always same as Vdd and the MCU operates in varying voltage levels.
+In contrast, our work demonstrates that accounting for sub-normal voltage operation is also critical in systems with regulated power supplies, which represent the majority of intermittent system setups.
 % Especially, this work reveals that these impacts come from the buffering effects of the inherent capacitance, which are not exist in these works.
-Also, we address the impacts of sub-normal voltage execution to correctness and efficiency of software designs, along with the suggestions to exploit such impacts.
+Also, we address the impacts of sub-normal voltage execution on the correctness and efficiency of software designs, along with suggestions to exploit such impacts for improved system performance.