2024d_execution_model/sections/OurApproach.tex

\section{Design Guidelines}
\label{sec:design_guidelines}

\subsection{Delay Checkpoint Execution}

The overhead of early checkpointing is considered small~\cite{choiCompilerDirected2022}.
For example, some static checkpointing~\cite{bhattiHarvOS2017} and WCET-based approaches~\cite{choiCompilerDirected2022,reymondSCHEMATIC2024} have explored strategy that 
WCET-based approaches can be extremely pessimistic~\cite{raffeckWoCA2024}.

\begin{figure}
    \centering
    \includegraphics[width=\linewidth]{figs/plot_expr_7_cropped.pdf}
    \caption{Execution times across various checkpoint voltages, normalized to the 3.4V case.}
    % \label{fig:hardware_setup}
\end{figure}

\subsection{Use Vdd and Known Voltage for Checkpoint Execution}
\label{sec:use_vdd}

Sec.~\ref{sec:predicting_power_failures} demonstrates that capacitor voltage is not a good estimate for the system's remaining execution time.
Instead, we propose using Vdd for accurate estimation for imminent power-off, as in works not having power management systems (Sec.~\ref{sec:related_work}).
Also, utilize a voltage reference with a known value.
Note that the reference voltage should be lower than the minimal operating voltage of MCU.
We propose two efficient implementations, each for dynamic and static checkpoint schemes.

T1 utilizes a on-chip comparator (available both in STM32L5 and MSP430).
Using a voltage divider with two resistors, Vdd is reduced so that the comparator is triggered when the target power-off voltage is reached.

T2 is setup for static checkpoint techniques, which poll the capacitor voltage to determine whether execute checkpoint or not.
Instead of reading the capacitor voltage, it reads the reference voltage.
As we discussed in Sec.~\ref{sec:sub_normal_execution}, the voltage remains same while the system executes at normal voltage but the value increases during sub-normal voltage execution.

% \begin{itemize}
%     \item T1 utilizes a on-chip comparator (available both in STM32L5 and MSP430) with a reference voltage.
%     \item T2.
% \end{itemize}

\begin{figure}
    \centering
    \begin{subfigure}{\linewidth}
        \includegraphics[width=\textwidth]{figs/plot_expr_10_cropped.pdf}
        \caption{Dynamic checkpointing (JIT).}
        % \label{fig:eval_voltage_trace}
        \vspace{7pt}
    \end{subfigure}
    \begin{subfigure}{\linewidth}
        \includegraphics[width=\textwidth]{figs/plot_expr_11_cropped.pdf}
        \caption{Static checkpointing.}
        % \label{fig:eval_adaptivenss_finished_tasks}
    \end{subfigure}
    \caption{Impact of precise checkpoint timings to the end-to-end execution times.}
    % \label{fig:sub_voltage_execution}
\end{figure}

\subsection{Design Checkpoint Techniques for Sufficient Power Duration}