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- \section{Related Work}
- \label{sec:related_work}
- This work can be compared to existing modeling-based approaches that estimate the timing or efficiency of intermittent systems~\cite{kimRapid2024,houTale2024,erataETAP2023,ghasemiPES2023,sanmiguelEH2018a,sanmiguelEH2018}.
- The primary focus of these works is identifying the most efficient design configurations (e.g., capacitor size, input power or checkpoint techniques~\cite{kimRapid2024}) for a given application.
- Zhan et al.~\cite{zhanExploring2022} especially examined the trade-offs between capacitor sizes and forward progress.
- However, these works assume that the entire energy discharged from the capacitor is utilized by computing system, overlooking the buffering effects addressed in this work.
- Furthermore, our work proposes several practical guidelines to improve the efficiency of existing techniques with minimal efforts.
- In some works that do not have a dedicated power management system and directly supply unregulated power to the computing system~\cite{balsamoHibernus2015,balsamoHibernus2016,netoDiCA2023,raffeckCO2CoDe2024,reymondEarlyBird2024}, $V_{dd}$ has been used as a checkpoint signal.
- This is natural in these works since the voltage of the energy storage is always identical to $V_{dd}$.
- % This is natural in these works since the voltage of the energy storage is always same as Vdd and the MCU operates in varying voltage levels.
- In contrast, our work demonstrates that accounting for sub-normal voltage operation is also critical in systems with regulated power supplies, which represent the majority of intermittent system setups.
- % Especially, this work reveals that these impacts come from the buffering effects of the inherent capacitance, which are not exist in these works.
- Also, we address the impacts of sub-normal voltage execution on the correctness and efficiency of software designs, along with suggestions to exploit such impacts for improved system performance.
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