2024d_execution_model/sections/OurModel.tex

\section{Detailed Intermittent Execution Model}

In this section, we describe a detailed execution model of intermittent systems based on our observations from the measurement.
In Sec.~\ref{sec:system_description}, we introduce the typical hardware setup of intermittent systems and the system we collected the data from.
Sec.~\ref{sec:execution_model} presents the key observations from our measurements and proposes our detailed execution model.

\subsection{System Description}
\label{sec:system_description}


\begin{figure}
    \centering
    \includegraphics[width=\linewidth]{figs/cropped/system.pdf}
    \caption{A typical hardware setup of intermittent systems.}
    \label{fig:hardware_setup}
\end{figure}

A typical intermittent system consists of two components: a power management system and a computing system.
Fig.~\ref{fig:hardware_setup} illustrates this setup.
The power management system is responsible for collecting the incoming power into energy storage and providing a stable-voltage current to the computing system.
The computing system equips NVMs along with the MCU and peripherals, and utilize the NVMs for state retention between power failures.

This setup has two notable decoupling capacitors that affect the execution model of intermittent systems.
The first one is attached to the power management system, as voltage regulators need a capacitor larger than the required capacitance for correct execution.
Also, the computing system also has a decoupling capacitor.

In this work, our goal is to model the buffering effects of these capacitors and evaluate their implications on software designs.
(Recent studies present the need for better computing capability~\cite{bakarProtean2023a})
For model validation and evaluation, we use a custom-built board equipped with an ARM Cortex-M33 core and XXMB of FRAM.
Our setup requires XXuF and 220uF capacitors for C1 and C2, respectively, for stable execution of checkpoint and recovery.
Sec.~\ref{sec:other_architectures} evaluates our model in different architectures.

\subsection{Execution Model}
\label{sec:execution_model}

\begin{figure}
    \centering
    \begin{subfigure}{\linewidth}
        \includegraphics[width=\textwidth]{figs/plot_expr_8a_cropped.pdf}
        \caption{Trace of one power cycle.}
        \label{fig:execution_trace_one_cycle}
        \vspace{5pt}
    \end{subfigure}
    \begin{subfigure}{\linewidth}
        \includegraphics[width=\textwidth]{figs/plot_expr_8b_cropped.pdf}
        \caption{Detailed trace.}
        \label{fig:execution_trace_detailed}
    \end{subfigure}
    \caption{Voltage measurement of capacitor and Vdd (470uF, 1.5mA current supply).}
    \label{fig:execution_trace}
\end{figure}

Fig.~\ref{fig:execution_trace} shows the voltage trace of the energy storage and the Vdd of the computing system.
A 470uF capacitor is used for the energy storage to generate execution of xx ms under 1.5mA current supply.
Fig.~\ref{fig:execution_trace_one_cycle} shows the trace during one power cycle, and Fig.~\ref{fig:execution_trace_detailed} presents the first execution cycle in more detail.

Three key observations that affect software designer's decision.

\begin{itemize}
    \item \textbf{O1}: The capacitor voltage drops quickly to charge decoupling capacitor when system wakes-up ($t1$--$t2$).
    \item \textbf{O2}: The system executes at sub-voltage using the decoupling capacitor, even after power supply stops ($t4$--$t5$).
    \item \textbf{O3}: The decoupling capacitor discharges while the system is powered-off (after $t5$).
\end{itemize}

\begin{figure}
    \centering
    \includegraphics[width=\linewidth]{figs/cropped/detailed_execution_model.pdf}
    \caption{Detailed execution model of intermittent systems.}
    \label{fig:detailed_execution_model}
\end{figure}

Fig.~\ref{fig:detailed_execution_model} shows our detailed execution model, which reflects all the key observations.

In the following sections, we discuss how this model benefits the software design.

\subsection{Impact on Power Efficiency}

The traditional model implies that power consumed between power-on and power-off thresholds are entirely used for the computing system (including hardware initialization and recovery).
However, our model reveals that huge energy is used for charging the decaps (\textbf{O1}) and discharged during power-off durations (\textbf{O3}).
This implies that much smaller energy is used for the useful computation compared to the designer's expectation.

\begin{figure}
    \centering
    \includegraphics[width=\linewidth]{figs/plot_expr_5_cropped.pdf}
    \caption{Distribution of energy consumed in a power cycle in different capacitor sizes (1mA current supply).}
    \label{fig:power_distribution}
\end{figure}

Fig.~\ref{fig:power_distribution} shows the distribution of the energy consumed for each stage of intermittent execution within one power cycle, averaged over XX executions, in various capacitor sizes. 
The line represents the average time of useful computation.
The checkpoint is executed by the interrupt from the power management system, which is generated when the capacitor voltage reaches the power-off threshold (3.4V).
Note that this is the last point for checkpoint execution according to the traditional model.

The results shows that significant energy is wasted in decoupling capacitor.
The cost is more expensive when the capacitor size is small since the decaps discharge rate follows the RC-discharging circuits.
While using smaller capacitors shortens the power-off durations, the discharging behavior penalizes them most since XX\% of energy is discharged at the first XX ms.

More importantly, this wasted energy is expected to be used for the computation in traditional execution model, as all the energy except for the initialization and checkpoint/recovery is expected to be used in computations.
It brings significant errors between the two models in available energy for the execution.
In 470uF case, the actual energy efficiency (Execution) and the expectation from the traditional model (Execution and Discharged) differs by XX times.

(Limitations of power failure injection and simulation based evaluations).

\subsection{Impact on Predicting Power Failures}

\begin{figure}
    \centering
    \begin{subfigure}{\linewidth}
        \includegraphics[width=\textwidth]{figs/plot_expr_6a_cropped.pdf}
        \caption{Input current is 1mA.}
        % \label{fig:eval_voltage_trace}
        \vspace{5pt}
    \end{subfigure}
    \begin{subfigure}{\linewidth}
        \includegraphics[width=\textwidth]{figs/plot_expr_6b_cropped.pdf}
        \caption{Input current is 3mA.}
        % \label{fig:eval_adaptivenss_finished_tasks}
    \end{subfigure}
    \caption{Ratio of sub-voltage operations in total execution time.}
    % \label{fig:}
\end{figure}

According to the traditional model, the system states should be saved to NVM before power-off threshold.
Our model shows that the system may operate after this point using the energy stored in the decaps (\textbf{O2}). 
As a result, the energy storage voltage is not a good approximate of the remaining time that system can execute.

\subsection{Impact of Sub-normal Voltage Execution}

The traditional model makes the software designers assume the system is executed under stable voltage.
However, the execution after the power-off threshold (\textbf{O3}) happens in sub-normal voltage.
Being aware of this is important to the software designers since the peripherals and analog components may function differently.

The two most critical examples are Analog-Digital Converter (ADC) and external memory.

\begin{figure}
    \centering
    \begin{subfigure}{0.45\linewidth}
        \includegraphics[width=\textwidth]{figs/plot_expr_2_cropped.pdf}
        \caption{Trace of one power cycle.}
        % \label{fig:eval_voltage_trace}
    \end{subfigure}
    \hfill
    \begin{subfigure}{0.52\linewidth}
        \includegraphics[width=\textwidth]{figs/plot_expr_3_cropped.pdf}
        \caption{Detailed trace.}
        % \label{fig:eval_adaptivenss_finished_tasks}
    \end{subfigure}
    \caption{Voltage of the capacitor and Vdd, sampled 470uF and 1.5mA.}
    % \label{fig:}
\end{figure}

\subsection{Sensitivity to Architectural Designs}
\label{sec:other_architectures}

Finally, we evaluate our model against two different architectural setups: MSP430 and Cortex-M33 with MRAM.
MSP430 has less computational capability than Cortex-M33 cores.
But it is a most popular platform for intermittent system researches, since it is a low-power system having on-chip FRAM.
We used MSP430FR5994 evaluation board, having 10uF of onboard decap.
For the second setup, we put MRAM to our evaluation platform instead of FRAM.
Core frequencies, capacitance of power management system, input power targeting xx ms execution.

\begin{figure}
    \centering
    \includegraphics[width=\linewidth]{figs/plot_expr_9_cropped.pdf}
    \caption{Energy breakdown and the ratio of sub-voltage operations in different architectures.}
    \label{fig:other_architectures}
\end{figure}

Fig.~\ref{fig:other_architectures} shows the results in different power-off voltage.
The bar in the left shows the energy breakdown in one power cycle, and the one in the right represents the ratio of the execution time operated in sub-voltage.