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- \section{Related Work}
- \label{sec:related_work}
- This work can be compared to the existing modeling-based approaches that estimate the latency or efficiency of the intermittent systems~\cite{kimRapid2024,houTale2024,erataETAP2023,ghasemiPES2023,sanmiguelEH2018a,sanmiguelEH2018}.
- The primary focus of these works is to find the most efficient design configurations (e.g., capacitor size, input power or checkpoint techniques~\cite{kimRapid2024}) for the given application.
- Zhan et al.~\cite{zhanExploring2022} especially focused on the tradeoff of capacitor size and the forward progress.
- However, the modelings in these works assume the entire energy discharged in the capacitor is used in the computing systems, overlooking the buffering effects that are addressed in this work.
- Furthermore, this work propose several practical guidelines that can improve the efficiency of the existing techniques with minimal efforts.
- In some works that do not have a dedicated power management system and directly supply unregulated power to the computing system~\cite{balsamoHibernus2015,balsamoHibernus2016,netoDiCA2023,raffeckCO2CoDe2024,reymondEarlyBird2024}, the MCU operating voltage (Vdd) has been used for checkpoint signals.
- This is natural in these works since the voltage of the energy storage is always same as Vdd and the MCU operates in varying voltage levels.
- On the other hand, our work demonstrates that considering sub-normal voltage operation is also important in the systems with a regulated power supply, which is the majority.
- % Especially, this work reveals that these impacts come from the buffering effects of the inherent capacitance, which are not exist in these works.
- Also, we address the impacts of sub-normal voltage execution to correctness and efficiency of software designs, along with the suggestions to exploit such impacts.
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