Add manual for CubeIDE

Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_spi.h

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+/**
+  ******************************************************************************
+  * @file    stm32l5xx_ll_spi.h
+  * @author  MCD Application Team
+  * @brief   Header file of SPI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_LL_SPI_H
+#define STM32L5xx_LL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx.h"
+
+/** @addtogroup STM32L5xx_LL_Driver
+  * @{
+  */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3)
+
+/** @defgroup SPI_LL SPI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  SPI Init structures definition
+  */
+typedef struct
+{
+  uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+
+  uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
+                                         This parameter can be a value of @ref SPI_LL_EC_MODE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+
+  uint32_t DataWidth;               /*!< Specifies the SPI data width.
+                                         This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+
+  uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+
+  uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_LL_EC_PHASE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+
+  uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
+                                         This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+
+  uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
+                                         @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+
+  uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+
+  uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
+                                         This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
+
+                                         This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+
+  uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+
+} LL_SPI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+  * @{
+  */
+
+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_SPI_ReadReg function
+  * @{
+  */
+#define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
+#define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
+#define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
+#define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
+#define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
+#define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
+#define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
+  * @{
+  */
+#define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
+#define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
+#define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_MODE Operation Mode
+  * @{
+  */
+#define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
+#define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
+  * @{
+  */
+#define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
+#define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
+#define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+  * @{
+  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
+  * @{
+  */
+#define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
+#define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+  * @{
+  */
+#define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
+#define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
+#define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
+  * @{
+  */
+#define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
+#define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
+#define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_SPI_DATAWIDTH_4BIT              (SPI_CR2_DS_0 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  4 bits */
+#define LL_SPI_DATAWIDTH_5BIT              (SPI_CR2_DS_2)                                              /*!< Data length for SPI transfer:  5 bits */
+#define LL_SPI_DATAWIDTH_6BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer:  6 bits */
+#define LL_SPI_DATAWIDTH_7BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  7 bits */
+#define LL_SPI_DATAWIDTH_8BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer:  8 bits */
+#define LL_SPI_DATAWIDTH_9BIT              (SPI_CR2_DS_3)                                              /*!< Data length for SPI transfer:  9 bits */
+#define LL_SPI_DATAWIDTH_10BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer: 10 bits */
+#define LL_SPI_DATAWIDTH_11BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer: 11 bits */
+#define LL_SPI_DATAWIDTH_12BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 12 bits */
+#define LL_SPI_DATAWIDTH_13BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2)                               /*!< Data length for SPI transfer: 13 bits */
+#define LL_SPI_DATAWIDTH_14BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 14 bits */
+#define LL_SPI_DATAWIDTH_15BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)                /*!< Data length for SPI transfer: 15 bits */
+#define LL_SPI_DATAWIDTH_16BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+  * @{
+  */
+#define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
+  * @{
+  */
+#define LL_SPI_CRC_8BIT                    0x00000000U               /*!<  8-bit CRC length */
+#define LL_SPI_CRC_16BIT                   (SPI_CR1_CRCL)            /*!< 16-bit CRC length */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
+  * @{
+  */
+#define LL_SPI_RX_FIFO_TH_HALF             0x00000000U               /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
+#define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit)  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
+  * @{
+  */
+#define LL_SPI_RX_FIFO_EMPTY               0x00000000U                       /*!< FIFO reception empty */
+#define LL_SPI_RX_FIFO_QUARTER_FULL        (SPI_SR_FRLVL_0)                  /*!< FIFO reception 1/4   */
+#define LL_SPI_RX_FIFO_HALF_FULL           (SPI_SR_FRLVL_1)                  /*!< FIFO reception 1/2   */
+#define LL_SPI_RX_FIFO_FULL                (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
+  * @{
+  */
+#define LL_SPI_TX_FIFO_EMPTY               0x00000000U                       /*!< FIFO transmission empty */
+#define LL_SPI_TX_FIFO_QUARTER_FULL        (SPI_SR_FTLVL_0)                  /*!< FIFO transmission 1/4   */
+#define LL_SPI_TX_FIFO_HALF_FULL           (SPI_SR_FTLVL_1)                  /*!< FIFO transmission 1/2   */
+#define LL_SPI_TX_FIFO_FULL                (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
+  * @{
+  */
+#define LL_SPI_DMA_PARITY_EVEN             0x00000000U   /*!< Select DMA parity Even */
+#define LL_SPI_DMA_PARITY_ODD              0x00000001U   /*!< Select DMA parity Odd  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+  * @{
+  */
+
+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in SPI register
+  * @param  __INSTANCE__ SPI Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in SPI register
+  * @param  __INSTANCE__ SPI Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+  * @{
+  */
+
+/** @defgroup SPI_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable SPI peripheral
+  * @rmtoll CR1          SPE           LL_SPI_Enable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+  * @brief  Disable SPI peripheral
+  * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
+  * @rmtoll CR1          SPE           LL_SPI_Disable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+  * @brief  Check if SPI peripheral is enabled
+  * @rmtoll CR1          SPE           LL_SPI_IsEnabled
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set SPI operation mode to Master or Slave
+  * @note   This bit should not be changed when communication is ongoing.
+  * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
+  *         CR1          SSI           LL_SPI_SetMode
+  * @param  SPIx SPI Instance
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_MODE_MASTER
+  *         @arg @ref LL_SPI_MODE_SLAVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
+}
+
+/**
+  * @brief  Get SPI operation mode (Master or Slave)
+  * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
+  *         CR1          SSI           LL_SPI_GetMode
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_MODE_MASTER
+  *         @arg @ref LL_SPI_MODE_SLAVE
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
+}
+
+/**
+  * @brief  Set serial protocol used
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR2          FRF           LL_SPI_SetStandard
+  * @param  SPIx SPI Instance
+  * @param  Standard This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+  *         @arg @ref LL_SPI_PROTOCOL_TI
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
+}
+
+/**
+  * @brief  Get serial protocol used
+  * @rmtoll CR2          FRF           LL_SPI_GetStandard
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+  *         @arg @ref LL_SPI_PROTOCOL_TI
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
+}
+
+/**
+  * @brief  Set clock phase
+  * @note   This bit should not be changed when communication is ongoing.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
+  * @param  SPIx SPI Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_PHASE_1EDGE
+  *         @arg @ref LL_SPI_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Get clock phase
+  * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_PHASE_1EDGE
+  *         @arg @ref LL_SPI_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
+}
+
+/**
+  * @brief  Set clock polarity
+  * @note   This bit should not be changed when communication is ongoing.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
+  * @param  SPIx SPI Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_POLARITY_LOW
+  *         @arg @ref LL_SPI_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Get clock polarity
+  * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_POLARITY_LOW
+  *         @arg @ref LL_SPI_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
+}
+
+/**
+  * @brief  Set baud rate prescaler
+  * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
+  * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
+  * @param  SPIx SPI Instance
+  * @param  BaudRate This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
+}
+
+/**
+  * @brief  Get baud rate prescaler
+  * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
+}
+
+/**
+  * @brief  Set transfer bit order
+  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+  * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
+  * @param  SPIx SPI Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_LSB_FIRST
+  *         @arg @ref LL_SPI_MSB_FIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Get transfer bit order
+  * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_LSB_FIRST
+  *         @arg @ref LL_SPI_MSB_FIRST
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
+}
+
+/**
+  * @brief  Set transfer direction mode
+  * @note   For Half-Duplex mode, Rx Direction is set by default.
+  *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
+  * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
+  *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
+  *         CR1          BIDIOE        LL_SPI_SetTransferDirection
+  * @param  SPIx SPI Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_FULL_DUPLEX
+  *         @arg @ref LL_SPI_SIMPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
+}
+
+/**
+  * @brief  Get transfer direction mode
+  * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
+  *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
+  *         CR1          BIDIOE        LL_SPI_GetTransferDirection
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_FULL_DUPLEX
+  *         @arg @ref LL_SPI_SIMPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
+}
+
+/**
+  * @brief  Set frame data width
+  * @rmtoll CR2          DS            LL_SPI_SetDataWidth
+  * @param  SPIx SPI Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_DATAWIDTH_4BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_5BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_6BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_7BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_9BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_10BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_11BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_12BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_13BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_14BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_15BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
+}
+
+/**
+  * @brief  Get frame data width
+  * @rmtoll CR2          DS            LL_SPI_GetDataWidth
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_DATAWIDTH_4BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_5BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_6BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_7BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_9BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_10BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_11BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_12BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_13BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_14BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_15BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
+}
+
+/**
+  * @brief  Set threshold of RXFIFO that triggers an RXNE event
+  * @rmtoll CR2          FRXTH         LL_SPI_SetRxFIFOThreshold
+  * @param  SPIx SPI Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
+  *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
+}
+
+/**
+  * @brief  Get threshold of RXFIFO that triggers an RXNE event
+  * @rmtoll CR2          FRXTH         LL_SPI_GetRxFIFOThreshold
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
+  *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_CRC_Management CRC Management
+  * @{
+  */
+
+/**
+  * @brief  Enable CRC
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+  * @brief  Disable CRC
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+  * @brief  Check if CRC is enabled
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set CRC Length
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCL          LL_SPI_SetCRCWidth
+  * @param  SPIx SPI Instance
+  * @param  CRCLength This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_CRC_8BIT
+  *         @arg @ref LL_SPI_CRC_16BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
+}
+
+/**
+  * @brief  Get CRC Length
+  * @rmtoll CR1          CRCL          LL_SPI_GetCRCWidth
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_CRC_8BIT
+  *         @arg @ref LL_SPI_CRC_16BIT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
+}
+
+/**
+  * @brief  Set CRCNext to transfer CRC on the line
+  * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
+  * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
+}
+
+/**
+  * @brief  Set polynomial for CRC calculation
+  * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
+  * @param  SPIx SPI Instance
+  * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+{
+  WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
+}
+
+/**
+  * @brief  Get polynomial for CRC calculation
+  * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
+  * @param  SPIx SPI Instance
+  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->CRCPR));
+}
+
+/**
+  * @brief  Get Rx CRC
+  * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
+  * @param  SPIx SPI Instance
+  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->RXCRCR));
+}
+
+/**
+  * @brief  Get Tx CRC
+  * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
+  * @param  SPIx SPI Instance
+  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->TXCRCR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
+  * @{
+  */
+
+/**
+  * @brief  Set NSS mode
+  * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
+  * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
+  * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
+  * @param  SPIx SPI Instance
+  * @param  NSS This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_NSS_SOFT
+  *         @arg @ref LL_SPI_NSS_HARD_INPUT
+  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
+  MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
+}
+
+/**
+  * @brief  Get NSS mode
+  * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
+  * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_NSS_SOFT
+  *         @arg @ref LL_SPI_NSS_HARD_INPUT
+  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+{
+  uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+  uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
+  return (Ssm | Ssoe);
+}
+
+/**
+  * @brief  Enable NSS pulse management
+  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+  * @rmtoll CR2          NSSP          LL_SPI_EnableNSSPulseMgt
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+  * @brief  Disable NSS pulse management
+  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+  * @rmtoll CR2          NSSP          LL_SPI_DisableNSSPulseMgt
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+  * @brief  Check if NSS pulse is enabled
+  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+  * @rmtoll CR2          NSSP          LL_SPI_IsEnabledNSSPulse
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Check if Rx buffer is not empty
+  * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Tx buffer is empty
+  * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get CRC error flag
+  * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get mode fault error flag
+  * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get overrun error flag
+  * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get busy flag
+  * @note   The BSY flag is cleared under any one of the following conditions:
+  * -When the SPI is correctly disabled
+  * -When a fault is detected in Master mode (MODF bit set to 1)
+  * -In Master mode, when it finishes a data transmission and no new data is ready to be
+  * sent
+  * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
+  * each data transfer.
+  * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get frame format error flag
+  * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get FIFO reception Level
+  * @rmtoll SR           FRLVL         LL_SPI_GetRxFIFOLevel
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_RX_FIFO_EMPTY
+  *         @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
+  *         @arg @ref LL_SPI_RX_FIFO_HALF_FULL
+  *         @arg @ref LL_SPI_RX_FIFO_FULL
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
+}
+
+/**
+  * @brief  Get FIFO Transmission Level
+  * @rmtoll SR           FTLVL         LL_SPI_GetTxFIFOLevel
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_TX_FIFO_EMPTY
+  *         @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
+  *         @arg @ref LL_SPI_TX_FIFO_HALF_FULL
+  *         @arg @ref LL_SPI_TX_FIFO_FULL
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
+}
+
+/**
+  * @brief  Clear CRC error flag
+  * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
+}
+
+/**
+  * @brief  Clear mode fault error flag
+  * @note   Clearing this flag is done by a read access to the SPIx_SR
+  *         register followed by a write access to the SPIx_CR1 register
+  * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg_sr;
+  tmpreg_sr = SPIx->SR;
+  (void) tmpreg_sr;
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+  * @brief  Clear overrun error flag
+  * @note   Clearing this flag is done by a read access to the SPIx_DR
+  *         register followed by a read access to the SPIx_SR register
+  * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = SPIx->DR;
+  (void) tmpreg;
+  tmpreg = SPIx->SR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear frame format error flag
+  * @note   Clearing this flag is done by reading SPIx_SR register
+  * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = SPIx->SR;
+  (void) tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
+  * @{
+  */
+
+/**
+  * @brief  Enable error interrupt
+  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+  * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+  * @brief  Enable Rx buffer not empty interrupt
+  * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+  * @brief  Enable Tx buffer empty interrupt
+  * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+  * @brief  Disable error interrupt
+  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+  * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+  * @brief  Disable Rx buffer not empty interrupt
+  * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+  * @brief  Disable Tx buffer empty interrupt
+  * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+  * @brief  Check if error interrupt is enabled
+  * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx buffer not empty interrupt is enabled
+  * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Tx buffer empty interrupt
+  * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Rx
+  * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA Rx
+  * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA Rx is enabled
+  * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Tx
+  * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA Tx
+  * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA Tx is enabled
+  * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set parity of  Last DMA reception
+  * @rmtoll CR2          LDMARX        LL_SPI_SetDMAParity_RX
+  * @param  SPIx SPI Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_DMA_PARITY_ODD
+  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
+}
+
+/**
+  * @brief  Get parity configuration for  Last DMA reception
+  * @rmtoll CR2          LDMARX        LL_SPI_GetDMAParity_RX
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_DMA_PARITY_ODD
+  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
+}
+
+/**
+  * @brief  Set parity of  Last DMA transmission
+  * @rmtoll CR2          LDMATX        LL_SPI_SetDMAParity_TX
+  * @param  SPIx SPI Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_DMA_PARITY_ODD
+  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
+}
+
+/**
+  * @brief  Get parity configuration for Last DMA transmission
+  * @rmtoll CR2          LDMATX        LL_SPI_GetDMAParity_TX
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_DMA_PARITY_ODD
+  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
+  * @param  SPIx SPI Instance
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+{
+  return (uint32_t) &(SPIx->DR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_DATA_Management DATA Management
+  * @{
+  */
+
+/**
+  * @brief  Read 8-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_ReceiveData8
+  * @param  SPIx SPI Instance
+  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+{
+  return (*((__IO uint8_t *)&SPIx->DR));
+}
+
+/**
+  * @brief  Read 16-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_ReceiveData16
+  * @param  SPIx SPI Instance
+  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+{
+  return (uint16_t)(READ_REG(SPIx->DR));
+}
+
+/**
+  * @brief  Write 8-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_TransmitData8
+  * @param  SPIx SPI Instance
+  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+{
+#if defined (__GNUC__)
+  __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
+  *spidr = TxData;
+#else
+  *((__IO uint8_t *)&SPIx->DR) = TxData;
+#endif /* __GNUC__ */
+}
+
+/**
+  * @brief  Write 16-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_TransmitData16
+  * @param  SPIx SPI Instance
+  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+#if defined (__GNUC__)
+  __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
+  *spidr = TxData;
+#else
+  SPIx->DR = TxData;
+#endif /* __GNUC__ */
+}
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_LL_SPI_H */
+

imc/docs/using_cube_IDE.md

@@ -0,0 +1,28 @@
+## CubeIDE 에서 인터미턴트 커널 활성화하기
+- `Core/Inc/ImC/imc_kernel.h` 내의 매크로 설정
+    - `#define imcUSE_IMC_KERNEL 1`: imc 커널 활성화
+    - `#define imcSTM32_CUBE_IDE 1`: CubeIDE 를 사용할 경우 1, `cmake` 환경일 경우 0
+        - 두 환경의 컴파일러가 생성하는 코드가 달라 서로 다른 레지스터를 사용하는 경우를 체크포인트 시 반영
+    - `#define imcSTACK_SIZE (1024)`: imc 응용의 스택 크기 (원소의 수) 선언
+        - 현재는 여러 imc task 가 있을 경우 동일한 스택 크기를 사용해야 함 (추후 업데이트 가능)
+- `Core/Src/main.c` 내의 task 생성 API 변경
+    - 기존 `osThreadNew()` 대신 `imcOsThreadNew()` 사용
+    - 파라미터는 동일
+- 응용 코드 내에서 체크포인트를 원하는 지점에 체크포인트 호출 매크로 (`imcREQUEST_CHECKPOINT()`) 삽입
+    - 예시:
+    ```c
+    void taskImcTest(void *argument) {
+        int i = 0;
+        while(1) {
+            osDelay(1000);
+            printf("i=%d\r\n", i++);
+            imcREQUEST_CHECKPOINT();
+        }
+    }
+    ```
+
+## FreeRTOS 코드를 재생성한 경우 변경사항 복구하기
+- 인터미턴트 커널 구현에는 일부 FreeRTOS 루틴의 변경이 필요 (`Middlewares/...`)
+- `.ioc` 파일 수정 등으로 코드를 재생성한 경우 변경사항이 제거됨
+- 코드 재생성 후 프로젝트 루트 디렉토리에서 `git checkout -- Middlewares/` 를 실행하여 커널 변경사항 복구
+- 이후 위 내용을 참고하여 `main.c` 파일의 필요한 부분 수정 

imc_freertos_app_m33.ioc

@@ -1,788 +1,788 @@
-#MicroXplorer Configuration settings - do not modify
-ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_1
-ADC1.CommonPathInternal=null|null|null|null
-ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,master,CommonPathInternal
-ADC1.NbrOfConversionFlag=1
-ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
-ADC1.Rank-0\#ChannelRegularConversion=1
-ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
-ADC1.master=1
-ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_2
-ADC2.CommonPathInternal=null|null|null|null
-ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,CommonPathInternal
-ADC2.NbrOfConversionFlag=1
-ADC2.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
-ADC2.Rank-0\#ChannelRegularConversion=1
-ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
-CAD.formats=
-CAD.pinconfig=
-CAD.provider=
-FDCAN1.CalculateBaudRateNominal=800000
-FDCAN1.CalculateTimeBitNominal=1250
-FDCAN1.CalculateTimeQuantumNominal=250.0
-FDCAN1.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal
-FMC.BusTurnAroundDuration1=2
-FMC.BusTurnAroundDuration2=2
-FMC.BusTurnAroundDuration3=2
-FMC.DataSetupTime1=30
-FMC.DataSetupTime2=30
-FMC.DataSetupTime3=30
-FMC.IPParameters=WriteOperation3,WriteOperation1,WriteOperation2,MaxChipSelectPulse3,DataSetupTime3,BusTurnAroundDuration3,DataSetupTime2,BusTurnAroundDuration2,DataSetupTime1,BusTurnAroundDuration1
-FMC.MaxChipSelectPulse3=DISABLE
-FMC.WriteOperation1=FMC_WRITE_OPERATION_ENABLE
-FMC.WriteOperation2=FMC_WRITE_OPERATION_ENABLE
-FMC.WriteOperation3=FMC_WRITE_OPERATION_ENABLE
-FREERTOS.FootprintOK=true
-FREERTOS.IPParameters=Tasks01,FootprintOK
-FREERTOS.Tasks01=taskEPS,24,256,taskEPSRunner,Default,NULL,Static,taskEPSBuffer,taskEPSControlBlock;taskSnap,48,512,taskSnapRunner,Default,NULL,Static,taskSnapBuffer,taskSnapControlBlock;taskAI,24,37968,taskAIRunner,Default,NULL,Static,taskAIBuffer,taskAIControlBlock
-File.Version=6
-GPIO.groupedBy=Group By Peripherals
-I2C1.IPParameters=Timing
-I2C1.Timing=0x00707CBB
-I2C3.IPParameters=Timing
-I2C3.Timing=0x00707CBB
-KeepUserPlacement=false
-Mcu.CPN=STM32L552ZET3
-Mcu.ContextProject=TrustZoneDisabled
-Mcu.Family=STM32L5
-Mcu.IP0=ADC1
-Mcu.IP1=ADC2
-Mcu.IP10=NVIC
-Mcu.IP11=PWR
-Mcu.IP12=RCC
-Mcu.IP13=SPI1
-Mcu.IP14=SPI2
-Mcu.IP15=SYS
-Mcu.IP16=TIM7
-Mcu.IP17=UART4
-Mcu.IP18=USART1
-Mcu.IP19=USART2
-Mcu.IP2=DEBUG
-Mcu.IP20=USART3
-Mcu.IP21=USB
-Mcu.IP22=USB_DEVICE
-Mcu.IP3=FDCAN1
-Mcu.IP4=FMC
-Mcu.IP5=FREERTOS
-Mcu.IP6=GTZC
-Mcu.IP7=I2C1
-Mcu.IP8=I2C3
-Mcu.IP9=ICACHE
-Mcu.IPNb=23
-Mcu.Name=STM32L552ZETx
-Mcu.Package=LQFP144
-Mcu.Pin0=PE2
-Mcu.Pin1=PE3
-Mcu.Pin10=PF2
-Mcu.Pin100=PB8
-Mcu.Pin101=PB9
-Mcu.Pin102=PE0
-Mcu.Pin103=PE1
-Mcu.Pin104=VP_FREERTOS_VS_CMSIS_V2
-Mcu.Pin105=VP_GTZC_VS_GTZC_Enable
-Mcu.Pin106=VP_ICACHE_VS_ICACHE
-Mcu.Pin107=VP_PWR_VS_DBSignals
-Mcu.Pin108=VP_PWR_VS_SECSignals
-Mcu.Pin109=VP_SYS_VS_tim2
-Mcu.Pin11=PF3
-Mcu.Pin110=VP_TIM7_VS_ClockSourceINT
-Mcu.Pin111=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS
-Mcu.Pin12=PF4
-Mcu.Pin13=PF5
-Mcu.Pin14=PF6
-Mcu.Pin15=PF7
-Mcu.Pin16=PF8
-Mcu.Pin17=PF9
-Mcu.Pin18=PF10
-Mcu.Pin19=PH0-OSC_IN (PH0)
-Mcu.Pin2=PE4
-Mcu.Pin20=PH1-OSC_OUT (PH1)
-Mcu.Pin21=PC0
-Mcu.Pin22=PC1
-Mcu.Pin23=PC2
-Mcu.Pin24=PC3
-Mcu.Pin25=PA0
-Mcu.Pin26=PA1
-Mcu.Pin27=PA2
-Mcu.Pin28=PA3
-Mcu.Pin29=PA4
-Mcu.Pin3=PE5
-Mcu.Pin30=PA5
-Mcu.Pin31=PA6
-Mcu.Pin32=PA7
-Mcu.Pin33=PC4
-Mcu.Pin34=PC5
-Mcu.Pin35=PB0
-Mcu.Pin36=PB1
-Mcu.Pin37=PB2
-Mcu.Pin38=PF11
-Mcu.Pin39=PF12
-Mcu.Pin4=PE6
-Mcu.Pin40=PF13
-Mcu.Pin41=PF14
-Mcu.Pin42=PF15
-Mcu.Pin43=PG0
-Mcu.Pin44=PG1
-Mcu.Pin45=PE7
-Mcu.Pin46=PE8
-Mcu.Pin47=PE9
-Mcu.Pin48=PE10
-Mcu.Pin49=PE11
-Mcu.Pin5=PC13
-Mcu.Pin50=PE12
-Mcu.Pin51=PE13
-Mcu.Pin52=PE14
-Mcu.Pin53=PE15
-Mcu.Pin54=PB10
-Mcu.Pin55=PB12
-Mcu.Pin56=PB13
-Mcu.Pin57=PB14
-Mcu.Pin58=PB15
-Mcu.Pin59=PD8
-Mcu.Pin6=PC14-OSC32_IN (PC14)
-Mcu.Pin60=PD9
-Mcu.Pin61=PD10
-Mcu.Pin62=PD11
-Mcu.Pin63=PD12
-Mcu.Pin64=PD13
-Mcu.Pin65=PD14
-Mcu.Pin66=PD15
-Mcu.Pin67=PG2
-Mcu.Pin68=PG3
-Mcu.Pin69=PG4
-Mcu.Pin7=PC15-OSC32_OUT (PC15)
-Mcu.Pin70=PG5
-Mcu.Pin71=PG6
-Mcu.Pin72=PG7
-Mcu.Pin73=PG8
-Mcu.Pin74=PC6
-Mcu.Pin75=PC7
-Mcu.Pin76=PA8
-Mcu.Pin77=PA9
-Mcu.Pin78=PA10
-Mcu.Pin79=PA11
-Mcu.Pin8=PF0
-Mcu.Pin80=PA12
-Mcu.Pin81=PA13 (JTMS/SWDIO)
-Mcu.Pin82=PA14 (JTCK/SWCLK)
-Mcu.Pin83=PD0
-Mcu.Pin84=PD1
-Mcu.Pin85=PD2
-Mcu.Pin86=PD3
-Mcu.Pin87=PD4
-Mcu.Pin88=PD5
-Mcu.Pin89=PD7
-Mcu.Pin9=PF1
-Mcu.Pin90=PG9
-Mcu.Pin91=PG10
-Mcu.Pin92=PG11
-Mcu.Pin93=PG12
-Mcu.Pin94=PG13
-Mcu.Pin95=PG14
-Mcu.Pin96=PG15
-Mcu.Pin97=PB5
-Mcu.Pin98=PB6
-Mcu.Pin99=PB7
-Mcu.PinsNb=112
-Mcu.ThirdPartyNb=0
-Mcu.UserConstants=
-Mcu.UserName=STM32L552ZETx
-MxCube.Version=6.9.0
-MxDb.Version=DB.6.0.90
-NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
-NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
-NVIC.ForceEnableDMAVector=true
-NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
-NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
-NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
-NVIC.PendSV_IRQn=true\:7\:0\:false\:false\:false\:true\:false\:false\:false
-NVIC.PriorityGroup=NVIC_PRIORITYGROUP_3
-NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
-NVIC.SavedPendsvIrqHandlerGenerated=true
-NVIC.SavedSvcallIrqHandlerGenerated=true
-NVIC.SavedSystickIrqHandlerGenerated=true
-NVIC.SysTick_IRQn=true\:7\:0\:false\:false\:false\:true\:false\:true\:false
-NVIC.TIM2_IRQn=true\:7\:0\:false\:false\:true\:false\:false\:true\:true
-NVIC.TimeBase=TIM2_IRQn
-NVIC.TimeBaseIP=TIM2
-NVIC.USB_FS_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
-NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
-PA0.GPIOParameters=GPIO_Speed
-PA0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PA0.Mode=Asynchronous
-PA0.Signal=UART4_TX
-PA1.GPIOParameters=GPIO_Speed
-PA1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PA1.Mode=Asynchronous
-PA1.Signal=UART4_RX
-PA10.GPIOParameters=GPIO_Speed
-PA10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PA10.Mode=Asynchronous
-PA10.Signal=USART1_RX
-PA11.Mode=Device
-PA11.Signal=USB_DM
-PA12.Mode=Device
-PA12.Signal=USB_DP
-PA13\ (JTMS/SWDIO).Mode=Serial_Wire
-PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
-PA14\ (JTCK/SWCLK).Mode=Serial_Wire
-PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
-PA2.GPIOParameters=GPIO_Speed
-PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PA2.Mode=Asynchronous
-PA2.Signal=USART2_TX
-PA3.GPIOParameters=GPIO_Speed
-PA3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PA3.Mode=Asynchronous
-PA3.Signal=USART2_RX
-PA4.Locked=true
-PA4.Mode=NSS_Signal_Hard_Output
-PA4.Signal=SPI1_NSS
-PA5.Locked=true
-PA5.Mode=Full_Duplex_Master
-PA5.Signal=SPI1_SCK
-PA6.Locked=true
-PA6.Mode=Full_Duplex_Master
-PA6.Signal=SPI1_MISO
-PA7.Locked=true
-PA7.Signal=ADCx_IN12
-PA8.Locked=true
-PA8.Signal=GPIO_Output
-PA9.GPIOParameters=GPIO_Speed
-PA9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PA9.Mode=Asynchronous
-PA9.Signal=USART1_TX
-PB0.Locked=true
-PB0.Signal=ADCx_IN15
-PB1.Locked=true
-PB1.Signal=ADCx_IN16
-PB10.GPIOParameters=GPIO_Speed
-PB10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PB10.Locked=true
-PB10.Mode=Asynchronous
-PB10.Signal=USART3_TX
-PB12.Locked=true
-PB12.Mode=NSS_Signal_Hard_Output
-PB12.Signal=SPI2_NSS
-PB13.Locked=true
-PB13.Mode=Full_Duplex_Master
-PB13.Signal=SPI2_SCK
-PB14.Locked=true
-PB14.Mode=Full_Duplex_Master
-PB14.Signal=SPI2_MISO
-PB15.Locked=true
-PB15.Mode=Full_Duplex_Master
-PB15.Signal=SPI2_MOSI
-PB2.Locked=true
-PB2.Signal=GPIO_Output
-PB5.Locked=true
-PB5.Mode=Full_Duplex_Master
-PB5.Signal=SPI1_MOSI
-PB6.Locked=true
-PB6.Mode=I2C
-PB6.Signal=I2C1_SCL
-PB7.Locked=true
-PB7.Mode=I2C
-PB7.Signal=I2C1_SDA
-PB8.Locked=true
-PB8.Mode=FDCAN_Activate
-PB8.Signal=FDCAN1_RX
-PB9.Locked=true
-PB9.Mode=FDCAN_Activate
-PB9.Signal=FDCAN1_TX
-PC0.Locked=true
-PC0.Signal=ADCx_IN1
-PC1.Locked=true
-PC1.Signal=ADCx_IN2
-PC13.Locked=true
-PC13.Signal=GPIO_Output
-PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator
-PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN
-PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator
-PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT
-PC2.Locked=true
-PC2.Signal=ADCx_IN3
-PC3.Locked=true
-PC3.Signal=ADCx_IN4
-PC4.Locked=true
-PC4.Signal=ADCx_IN13
-PC5.GPIOParameters=GPIO_Speed
-PC5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PC5.Locked=true
-PC5.Mode=Asynchronous
-PC5.Signal=USART3_RX
-PC6.Locked=true
-PC6.Signal=GPIO_Output
-PC7.GPIOParameters=GPIO_Speed,GPIO_PuPd
-PC7.GPIO_PuPd=GPIO_NOPULL
-PC7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PC7.Locked=true
-PC7.Signal=GPIO_Output
-PD0.Signal=FMC_D2_DA2
-PD1.Signal=FMC_D3_DA3
-PD10.Signal=FMC_D15_DA15
-PD11.Signal=FMC_A16_CLE
-PD12.Signal=FMC_A17_ALE
-PD13.Signal=FMC_A18
-PD14.Signal=FMC_D0_DA0
-PD15.Signal=FMC_D1_DA1
-PD2.Locked=true
-PD2.Signal=SDMMC1_CMD
-PD3.Locked=true
-PD3.Signal=GPIO_Output
-PD4.Signal=FMC_NOE
-PD5.Signal=FMC_NWE
-PD7.Mode=NorPsramChipSelect1_1
-PD7.Signal=FMC_NE1
-PD8.Signal=FMC_D13_DA13
-PD9.Signal=FMC_D14_DA14
-PE0.Signal=FMC_NBL0
-PE1.Signal=FMC_NBL1
-PE10.Signal=FMC_D7_DA7
-PE11.Signal=FMC_D8_DA8
-PE12.Signal=FMC_D9_DA9
-PE13.Signal=FMC_D10_DA10
-PE14.Signal=FMC_D11_DA11
-PE15.Signal=FMC_D12_DA12
-PE2.Signal=FMC_A23
-PE3.Signal=FMC_A19
-PE4.Signal=FMC_A20
-PE5.Signal=FMC_A21
-PE6.Signal=FMC_A22
-PE7.Signal=FMC_D4_DA4
-PE8.Signal=FMC_D5_DA5
-PE9.Signal=FMC_D6_DA6
-PF0.Signal=FMC_A0
-PF1.Signal=FMC_A1
-PF10.GPIOParameters=GPIO_PuPd
-PF10.GPIO_PuPd=GPIO_NOPULL
-PF10.Locked=true
-PF10.Signal=GPIO_Input
-PF11.GPIOParameters=GPIO_PuPd
-PF11.GPIO_PuPd=GPIO_NOPULL
-PF11.Locked=true
-PF11.Signal=GPIO_Output
-PF12.Signal=FMC_A6
-PF13.Signal=FMC_A7
-PF14.Signal=FMC_A8
-PF15.Signal=FMC_A9
-PF2.Signal=FMC_A2
-PF3.Signal=FMC_A3
-PF4.Signal=FMC_A4
-PF5.Signal=FMC_A5
-PF6.Locked=true
-PF6.Signal=GPIO_Output
-PF7.Locked=true
-PF7.Signal=GPIO_Output
-PF8.GPIOParameters=GPIO_PuPd
-PF8.GPIO_PuPd=GPIO_NOPULL
-PF8.Locked=true
-PF8.Signal=GPIO_Input
-PF9.GPIOParameters=GPIO_PuPd
-PF9.GPIO_PuPd=GPIO_NOPULL
-PF9.Locked=true
-PF9.Signal=GPIO_Input
-PG0.Signal=FMC_A10
-PG1.Signal=FMC_A11
-PG10.Mode=NorPsramChipSelect3_3
-PG10.Signal=FMC_NE3
-PG11.GPIOParameters=GPIO_Speed,GPIO_PuPd
-PG11.GPIO_PuPd=GPIO_NOPULL
-PG11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PG11.Locked=true
-PG11.Signal=GPIO_Output
-PG12.Mode=NorPsramChipSelect4_4
-PG12.Signal=FMC_NE4
-PG13.Locked=true
-PG13.Signal=FMC_A24
-PG14.Locked=true
-PG14.Signal=FMC_A25
-PG15.Locked=true
-PG15.Signal=GPIO_Output
-PG2.Signal=FMC_A12
-PG3.Signal=FMC_A13
-PG4.Signal=FMC_A14
-PG5.Signal=FMC_A15
-PG6.Locked=true
-PG6.Signal=GPIO_Output
-PG7.Locked=true
-PG7.Mode=I2C
-PG7.Signal=I2C3_SCL
-PG8.Locked=true
-PG8.Mode=I2C
-PG8.Signal=I2C3_SDA
-PG9.Mode=NorPsramChipSelect2_2
-PG9.Signal=FMC_NE2
-PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
-PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
-PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
-PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
-PinOutPanel.RotationAngle=0
-ProjectManager.AskForMigrate=true
-ProjectManager.BackupPrevious=false
-ProjectManager.CompilerOptimize=6
-ProjectManager.ComputerToolchain=false
-ProjectManager.CoupleFile=false
-ProjectManager.CustomerFirmwarePackage=
-ProjectManager.DefaultFWLocation=true
-ProjectManager.DeletePrevious=true
-ProjectManager.DeviceId=STM32L552ZETx
-ProjectManager.FirmwarePackage=STM32Cube FW_L5 V1.5.0
-ProjectManager.FreePins=false
-ProjectManager.HalAssertFull=false
-ProjectManager.HeapSize=0x200
-ProjectManager.KeepUserCode=true
-ProjectManager.LastFirmware=true
-ProjectManager.LibraryCopy=1
-ProjectManager.MainLocation=Core/Src
-ProjectManager.NoMain=false
-ProjectManager.PreviousToolchain=STM32CubeIDE
-ProjectManager.ProjectBuild=false
-ProjectManager.ProjectFileName=imc_freertos_app_m33.ioc
-ProjectManager.ProjectName=imc_freertos_app_m33
-ProjectManager.ProjectStructure=
-ProjectManager.RegisterCallBack=
-ProjectManager.StackSize=0x400
-ProjectManager.TargetToolchain=STM32CubeIDE
-ProjectManager.ToolChainLocation=
-ProjectManager.UAScriptAfterPath=
-ProjectManager.UAScriptBeforePath=
-ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_FDCAN1_Init-FDCAN1-false-HAL-true,5-MX_FMC_Init-FMC-false-HAL-true,6-MX_I2C1_Init-I2C1-false-HAL-true,7-MX_I2C3_Init-I2C3-false-HAL-true,8-MX_SPI1_Init-SPI1-false-HAL-true,9-MX_SPI2_Init-SPI2-false-HAL-true,10-MX_TIM7_Init-TIM7-false-HAL-true,11-MX_UART4_Init-UART4-false-HAL-true,12-MX_USART1_UART_Init-USART1-false-HAL-true,13-MX_USART2_UART_Init-USART2-false-HAL-true,14-MX_USART3_UART_Init-USART3-false-HAL-true,15-MX_ICACHE_Init-ICACHE-false-HAL-true,16-MX_USB_Device_Init-USB_DEVICE-false-HAL-false,17-MX_GTZC_Init-GTZC-false-HAL-true,18-MX_ADC2_Init-ADC2-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true
-RCC.ADCFreq_Value=48000000
-RCC.AHBCLKDivider=RCC_SYSCLK_DIV2
-RCC.AHBFreq_Value=32000000
-RCC.APB1Freq_Value=32000000
-RCC.APB1TimFreq_Value=32000000
-RCC.APB2Freq_Value=32000000
-RCC.APB2TimFreq_Value=32000000
-RCC.CRSFreq_Value=48000000
-RCC.CortexFreq_Value=32000000
-RCC.DFSDMFreq_Value=32000000
-RCC.FCLKCortexFreq_Value=32000000
-RCC.FDCANFreq_Value=64000000
-RCC.FamilyName=M
-RCC.HCLKFreq_Value=32000000
-RCC.HSE_VALUE=16000000
-RCC.HSI48_VALUE=48000000
-RCC.HSI_VALUE=16000000
-RCC.I2C1Freq_Value=32000000
-RCC.I2C2Freq_Value=32000000
-RCC.I2C3Freq_Value=32000000
-RCC.I2C4Freq_Value=32000000
-RCC.IPParameters=ADCFreq_Value,AHBCLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,OCTOSPIMFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQ,PLLQoutputFreq_Value,PLLR,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value,WatchDogFreq_Value
-RCC.LPTIM1Freq_Value=32000000
-RCC.LPTIM2Freq_Value=32000000
-RCC.LPTIM3Freq_Value=32000000
-RCC.LPUART1Freq_Value=32000000
-RCC.LSCOPinFreq_Value=32000
-RCC.LSI_VALUE=32000
-RCC.MCO1PinFreq_Value=64000000
-RCC.MSI_VALUE=4000000
-RCC.OCTOSPIMFreq_Value=64000000
-RCC.PLLN=16
-RCC.PLLPoutputFreq_Value=36571428.571428575
-RCC.PLLQ=RCC_PLLQ_DIV4
-RCC.PLLQoutputFreq_Value=64000000
-RCC.PLLR=RCC_PLLR_DIV4
-RCC.PLLRCLKFreq_Value=64000000
-RCC.PLLSAI1N=24
-RCC.PLLSAI1PoutputFreq_Value=13714285.714285715
-RCC.PLLSAI1QoutputFreq_Value=48000000
-RCC.PLLSAI1RoutputFreq_Value=48000000
-RCC.PLLSAI2PoutputFreq_Value=4571428.571428572
-RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
-RCC.PWRFreq_Value=64000000
-RCC.RNGFreq_Value=48000000
-RCC.RTCFreq_Value=32000
-RCC.SAI1Freq_Value=13714285.714285715
-RCC.SAI2Freq_Value=13714285.714285715
-RCC.SDMMCFreq_Value=36571428.571428575
-RCC.SYSCLKFreq_VALUE=64000000
-RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
-RCC.UART4Freq_Value=32000000
-RCC.UART5Freq_Value=32000000
-RCC.USART1Freq_Value=32000000
-RCC.USART2Freq_Value=32000000
-RCC.USART3Freq_Value=32000000
-RCC.USBFreq_Value=48000000
-RCC.VCOInput2Freq_Value=4000000
-RCC.VCOInput3Freq_Value=4000000
-RCC.VCOInputFreq_Value=16000000
-RCC.VCOOutputFreq_Value=256000000
-RCC.VCOSAI1OutputFreq_Value=96000000
-RCC.VCOSAI2OutputFreq_Value=32000000
-RCC.WatchDogFreq_Value=32000
-SH.ADCx_IN1.0=ADC1_IN1,IN1-Single-Ended
-SH.ADCx_IN1.ConfNb=1
-SH.ADCx_IN12.0=ADC1_IN12
-SH.ADCx_IN12.ConfNb=1
-SH.ADCx_IN13.0=ADC1_IN13
-SH.ADCx_IN13.ConfNb=1
-SH.ADCx_IN15.0=ADC1_IN15
-SH.ADCx_IN15.ConfNb=1
-SH.ADCx_IN16.0=ADC1_IN16
-SH.ADCx_IN16.ConfNb=1
-SH.ADCx_IN2.0=ADC1_IN2
-SH.ADCx_IN2.1=ADC2_IN2,IN2-Single-Ended
-SH.ADCx_IN2.ConfNb=2
-SH.ADCx_IN3.0=ADC1_IN3
-SH.ADCx_IN3.ConfNb=1
-SH.ADCx_IN4.0=ADC1_IN4
-SH.ADCx_IN4.ConfNb=1
-SH.FMC_A0.0=FMC_A0,24b-a2
-SH.FMC_A0.1=FMC_A0,21b-a1
-SH.FMC_A0.2=FMC_A0,20b-a3
-SH.FMC_A0.3=FMC_A0,20b-a4
-SH.FMC_A0.ConfNb=4
-SH.FMC_A1.0=FMC_A1,24b-a2
-SH.FMC_A1.1=FMC_A1,21b-a1
-SH.FMC_A1.2=FMC_A1,20b-a3
-SH.FMC_A1.3=FMC_A1,20b-a4
-SH.FMC_A1.ConfNb=4
-SH.FMC_A10.0=FMC_A10,24b-a2
-SH.FMC_A10.1=FMC_A10,21b-a1
-SH.FMC_A10.2=FMC_A10,20b-a3
-SH.FMC_A10.3=FMC_A10,20b-a4
-SH.FMC_A10.ConfNb=4
-SH.FMC_A11.0=FMC_A11,24b-a2
-SH.FMC_A11.1=FMC_A11,21b-a1
-SH.FMC_A11.2=FMC_A11,20b-a3
-SH.FMC_A11.3=FMC_A11,20b-a4
-SH.FMC_A11.ConfNb=4
-SH.FMC_A12.0=FMC_A12,24b-a2
-SH.FMC_A12.1=FMC_A12,21b-a1
-SH.FMC_A12.2=FMC_A12,20b-a3
-SH.FMC_A12.3=FMC_A12,20b-a4
-SH.FMC_A12.ConfNb=4
-SH.FMC_A13.0=FMC_A13,24b-a2
-SH.FMC_A13.1=FMC_A13,21b-a1
-SH.FMC_A13.2=FMC_A13,20b-a3
-SH.FMC_A13.3=FMC_A13,20b-a4
-SH.FMC_A13.ConfNb=4
-SH.FMC_A14.0=FMC_A14,24b-a2
-SH.FMC_A14.1=FMC_A14,21b-a1
-SH.FMC_A14.2=FMC_A14,20b-a3
-SH.FMC_A14.3=FMC_A14,20b-a4
-SH.FMC_A14.ConfNb=4
-SH.FMC_A15.0=FMC_A15,24b-a2
-SH.FMC_A15.1=FMC_A15,21b-a1
-SH.FMC_A15.2=FMC_A15,20b-a3
-SH.FMC_A15.3=FMC_A15,20b-a4
-SH.FMC_A15.ConfNb=4
-SH.FMC_A16_CLE.0=FMC_A16,24b-a2
-SH.FMC_A16_CLE.1=FMC_A16,21b-a1
-SH.FMC_A16_CLE.2=FMC_A16,20b-a3
-SH.FMC_A16_CLE.3=FMC_A16,20b-a4
-SH.FMC_A16_CLE.ConfNb=4
-SH.FMC_A17_ALE.0=FMC_A17,24b-a2
-SH.FMC_A17_ALE.1=FMC_A17,21b-a1
-SH.FMC_A17_ALE.2=FMC_A17,20b-a3
-SH.FMC_A17_ALE.3=FMC_A17,20b-a4
-SH.FMC_A17_ALE.ConfNb=4
-SH.FMC_A18.0=FMC_A18,24b-a2
-SH.FMC_A18.1=FMC_A18,21b-a1
-SH.FMC_A18.2=FMC_A18,20b-a3
-SH.FMC_A18.3=FMC_A18,20b-a4
-SH.FMC_A18.ConfNb=4
-SH.FMC_A19.0=FMC_A19,24b-a2
-SH.FMC_A19.1=FMC_A19,21b-a1
-SH.FMC_A19.2=FMC_A19,20b-a3
-SH.FMC_A19.3=FMC_A19,20b-a4
-SH.FMC_A19.ConfNb=4
-SH.FMC_A2.0=FMC_A2,24b-a2
-SH.FMC_A2.1=FMC_A2,21b-a1
-SH.FMC_A2.2=FMC_A2,20b-a3
-SH.FMC_A2.3=FMC_A2,20b-a4
-SH.FMC_A2.ConfNb=4
-SH.FMC_A20.0=FMC_A20,24b-a2
-SH.FMC_A20.1=FMC_A20,21b-a1
-SH.FMC_A20.ConfNb=2
-SH.FMC_A21.0=FMC_A21,24b-a2
-SH.FMC_A21.ConfNb=1
-SH.FMC_A22.0=FMC_A22,24b-a2
-SH.FMC_A22.ConfNb=1
-SH.FMC_A23.0=FMC_A23,24b-a2
-SH.FMC_A23.ConfNb=1
-SH.FMC_A24.0=FMC_A24
-SH.FMC_A24.ConfNb=1
-SH.FMC_A25.0=FMC_A25
-SH.FMC_A25.ConfNb=1
-SH.FMC_A3.0=FMC_A3,24b-a2
-SH.FMC_A3.1=FMC_A3,21b-a1
-SH.FMC_A3.2=FMC_A3,20b-a3
-SH.FMC_A3.3=FMC_A3,20b-a4
-SH.FMC_A3.ConfNb=4
-SH.FMC_A4.0=FMC_A4,24b-a2
-SH.FMC_A4.1=FMC_A4,21b-a1
-SH.FMC_A4.2=FMC_A4,20b-a3
-SH.FMC_A4.3=FMC_A4,20b-a4
-SH.FMC_A4.ConfNb=4
-SH.FMC_A5.0=FMC_A5,24b-a2
-SH.FMC_A5.1=FMC_A5,21b-a1
-SH.FMC_A5.2=FMC_A5,20b-a3
-SH.FMC_A5.3=FMC_A5,20b-a4
-SH.FMC_A5.ConfNb=4
-SH.FMC_A6.0=FMC_A6,24b-a2
-SH.FMC_A6.1=FMC_A6,21b-a1
-SH.FMC_A6.2=FMC_A6,20b-a3
-SH.FMC_A6.3=FMC_A6,20b-a4
-SH.FMC_A6.ConfNb=4
-SH.FMC_A7.0=FMC_A7,24b-a2
-SH.FMC_A7.1=FMC_A7,21b-a1
-SH.FMC_A7.2=FMC_A7,20b-a3
-SH.FMC_A7.3=FMC_A7,20b-a4
-SH.FMC_A7.ConfNb=4
-SH.FMC_A8.0=FMC_A8,24b-a2
-SH.FMC_A8.1=FMC_A8,21b-a1
-SH.FMC_A8.2=FMC_A8,20b-a3
-SH.FMC_A8.3=FMC_A8,20b-a4
-SH.FMC_A8.ConfNb=4
-SH.FMC_A9.0=FMC_A9,24b-a2
-SH.FMC_A9.1=FMC_A9,21b-a1
-SH.FMC_A9.2=FMC_A9,20b-a3
-SH.FMC_A9.3=FMC_A9,20b-a4
-SH.FMC_A9.ConfNb=4
-SH.FMC_D0_DA0.0=FMC_D0,16b-d1
-SH.FMC_D0_DA0.1=FMC_D0,16b-d2
-SH.FMC_D0_DA0.2=FMC_D0,16b-d3
-SH.FMC_D0_DA0.3=FMC_D0,16b-d4
-SH.FMC_D0_DA0.ConfNb=4
-SH.FMC_D10_DA10.0=FMC_D10,16b-d1
-SH.FMC_D10_DA10.1=FMC_D10,16b-d2
-SH.FMC_D10_DA10.2=FMC_D10,16b-d3
-SH.FMC_D10_DA10.3=FMC_D10,16b-d4
-SH.FMC_D10_DA10.ConfNb=4
-SH.FMC_D11_DA11.0=FMC_D11,16b-d1
-SH.FMC_D11_DA11.1=FMC_D11,16b-d2
-SH.FMC_D11_DA11.2=FMC_D11,16b-d3
-SH.FMC_D11_DA11.3=FMC_D11,16b-d4
-SH.FMC_D11_DA11.ConfNb=4
-SH.FMC_D12_DA12.0=FMC_D12,16b-d1
-SH.FMC_D12_DA12.1=FMC_D12,16b-d2
-SH.FMC_D12_DA12.2=FMC_D12,16b-d3
-SH.FMC_D12_DA12.3=FMC_D12,16b-d4
-SH.FMC_D12_DA12.ConfNb=4
-SH.FMC_D13_DA13.0=FMC_D13,16b-d1
-SH.FMC_D13_DA13.1=FMC_D13,16b-d2
-SH.FMC_D13_DA13.2=FMC_D13,16b-d3
-SH.FMC_D13_DA13.3=FMC_D13,16b-d4
-SH.FMC_D13_DA13.ConfNb=4
-SH.FMC_D14_DA14.0=FMC_D14,16b-d1
-SH.FMC_D14_DA14.1=FMC_D14,16b-d2
-SH.FMC_D14_DA14.2=FMC_D14,16b-d3
-SH.FMC_D14_DA14.3=FMC_D14,16b-d4
-SH.FMC_D14_DA14.ConfNb=4
-SH.FMC_D15_DA15.0=FMC_D15,16b-d1
-SH.FMC_D15_DA15.1=FMC_D15,16b-d2
-SH.FMC_D15_DA15.2=FMC_D15,16b-d3
-SH.FMC_D15_DA15.3=FMC_D15,16b-d4
-SH.FMC_D15_DA15.ConfNb=4
-SH.FMC_D1_DA1.0=FMC_D1,16b-d1
-SH.FMC_D1_DA1.1=FMC_D1,16b-d2
-SH.FMC_D1_DA1.2=FMC_D1,16b-d3
-SH.FMC_D1_DA1.3=FMC_D1,16b-d4
-SH.FMC_D1_DA1.ConfNb=4
-SH.FMC_D2_DA2.0=FMC_D2,16b-d1
-SH.FMC_D2_DA2.1=FMC_D2,16b-d2
-SH.FMC_D2_DA2.2=FMC_D2,16b-d3
-SH.FMC_D2_DA2.3=FMC_D2,16b-d4
-SH.FMC_D2_DA2.ConfNb=4
-SH.FMC_D3_DA3.0=FMC_D3,16b-d1
-SH.FMC_D3_DA3.1=FMC_D3,16b-d2
-SH.FMC_D3_DA3.2=FMC_D3,16b-d3
-SH.FMC_D3_DA3.3=FMC_D3,16b-d4
-SH.FMC_D3_DA3.ConfNb=4
-SH.FMC_D4_DA4.0=FMC_D4,16b-d1
-SH.FMC_D4_DA4.1=FMC_D4,16b-d2
-SH.FMC_D4_DA4.2=FMC_D4,16b-d3
-SH.FMC_D4_DA4.3=FMC_D4,16b-d4
-SH.FMC_D4_DA4.ConfNb=4
-SH.FMC_D5_DA5.0=FMC_D5,16b-d1
-SH.FMC_D5_DA5.1=FMC_D5,16b-d2
-SH.FMC_D5_DA5.2=FMC_D5,16b-d3
-SH.FMC_D5_DA5.3=FMC_D5,16b-d4
-SH.FMC_D5_DA5.ConfNb=4
-SH.FMC_D6_DA6.0=FMC_D6,16b-d1
-SH.FMC_D6_DA6.1=FMC_D6,16b-d2
-SH.FMC_D6_DA6.2=FMC_D6,16b-d3
-SH.FMC_D6_DA6.3=FMC_D6,16b-d4
-SH.FMC_D6_DA6.ConfNb=4
-SH.FMC_D7_DA7.0=FMC_D7,16b-d1
-SH.FMC_D7_DA7.1=FMC_D7,16b-d2
-SH.FMC_D7_DA7.2=FMC_D7,16b-d3
-SH.FMC_D7_DA7.3=FMC_D7,16b-d4
-SH.FMC_D7_DA7.ConfNb=4
-SH.FMC_D8_DA8.0=FMC_D8,16b-d1
-SH.FMC_D8_DA8.1=FMC_D8,16b-d2
-SH.FMC_D8_DA8.2=FMC_D8,16b-d3
-SH.FMC_D8_DA8.3=FMC_D8,16b-d4
-SH.FMC_D8_DA8.ConfNb=4
-SH.FMC_D9_DA9.0=FMC_D9,16b-d1
-SH.FMC_D9_DA9.1=FMC_D9,16b-d2
-SH.FMC_D9_DA9.2=FMC_D9,16b-d3
-SH.FMC_D9_DA9.3=FMC_D9,16b-d4
-SH.FMC_D9_DA9.ConfNb=4
-SH.FMC_NBL0.0=FMC_NBL0,2ByteEnable1
-SH.FMC_NBL0.1=FMC_NBL0,2ByteEnable2
-SH.FMC_NBL0.2=FMC_NBL0,2ByteEnable3
-SH.FMC_NBL0.3=FMC_NBL0,2ByteEnable4
-SH.FMC_NBL0.ConfNb=4
-SH.FMC_NBL1.0=FMC_NBL1,2ByteEnable1
-SH.FMC_NBL1.1=FMC_NBL1,2ByteEnable2
-SH.FMC_NBL1.2=FMC_NBL1,2ByteEnable3
-SH.FMC_NBL1.3=FMC_NBL1,2ByteEnable4
-SH.FMC_NBL1.ConfNb=4
-SH.FMC_NOE.0=FMC_NOE,Sram1
-SH.FMC_NOE.1=FMC_NOE,Sram2
-SH.FMC_NOE.2=FMC_NOE,Sram4
-SH.FMC_NOE.3=FMC_NOE,Psram3
-SH.FMC_NOE.ConfNb=4
-SH.FMC_NWE.0=FMC_NWE,Sram1
-SH.FMC_NWE.1=FMC_NWE,Sram2
-SH.FMC_NWE.2=FMC_NWE,Sram4
-SH.FMC_NWE.3=FMC_NWE,Psram3
-SH.FMC_NWE.ConfNb=4
-SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2
-SPI1.CalculateBaudRate=16.0 MBits/s
-SPI1.Direction=SPI_DIRECTION_2LINES
-SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS,BaudRatePrescaler
-SPI1.Mode=SPI_MODE_MASTER
-SPI1.VirtualNSS=VM_NSSHARD
-SPI1.VirtualType=VM_MASTER
-SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2
-SPI2.CalculateBaudRate=16.0 MBits/s
-SPI2.Direction=SPI_DIRECTION_2LINES
-SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS,BaudRatePrescaler
-SPI2.Mode=SPI_MODE_MASTER
-SPI2.VirtualNSS=VM_NSSHARD
-SPI2.VirtualType=VM_MASTER
-USART1.IPParameters=VirtualMode-Asynchronous
-USART1.VirtualMode-Asynchronous=VM_ASYNC
-USART2.IPParameters=VirtualMode-Asynchronous
-USART2.VirtualMode-Asynchronous=VM_ASYNC
-USART3.IPParameters=VirtualMode-Asynchronous
-USART3.VirtualMode-Asynchronous=VM_ASYNC
-USB_DEVICE.CLASS_NAME_FS=CDC
-USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS
-USB_DEVICE.VirtualMode=Cdc
-USB_DEVICE.VirtualModeFS=Cdc_FS
-VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
-VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
-VP_GTZC_VS_GTZC_Enable.Mode=GTZC_Enable
-VP_GTZC_VS_GTZC_Enable.Signal=GTZC_VS_GTZC_Enable
-VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache
-VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE
-VP_PWR_VS_DBSignals.Mode=DisableDeadBatterySignals
-VP_PWR_VS_DBSignals.Signal=PWR_VS_DBSignals
-VP_PWR_VS_SECSignals.Mode=Security/Privilege
-VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals
-VP_SYS_VS_tim2.Mode=TIM2
-VP_SYS_VS_tim2.Signal=SYS_VS_tim2
-VP_TIM7_VS_ClockSourceINT.Mode=Enable_Timer
-VP_TIM7_VS_ClockSourceINT.Signal=TIM7_VS_ClockSourceINT
-VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS
-VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_FS
-board=custom
-rtos.0.ip=FREERTOS
-isbadioc=false
+#MicroXplorer Configuration settings - do not modify
+ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_1
+ADC1.CommonPathInternal=null|null|null|null
+ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,master,CommonPathInternal
+ADC1.NbrOfConversionFlag=1
+ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC1.Rank-0\#ChannelRegularConversion=1
+ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
+ADC1.master=1
+ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_2
+ADC2.CommonPathInternal=null|null|null|null
+ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,CommonPathInternal
+ADC2.NbrOfConversionFlag=1
+ADC2.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC2.Rank-0\#ChannelRegularConversion=1
+ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
+FDCAN1.CalculateBaudRateNominal=800000
+FDCAN1.CalculateTimeBitNominal=1250
+FDCAN1.CalculateTimeQuantumNominal=250.0
+FDCAN1.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal
+FMC.BusTurnAroundDuration1=2
+FMC.BusTurnAroundDuration2=2
+FMC.BusTurnAroundDuration3=2
+FMC.DataSetupTime1=30
+FMC.DataSetupTime2=30
+FMC.DataSetupTime3=30
+FMC.IPParameters=WriteOperation3,WriteOperation1,WriteOperation2,MaxChipSelectPulse3,DataSetupTime3,BusTurnAroundDuration3,DataSetupTime2,BusTurnAroundDuration2,DataSetupTime1,BusTurnAroundDuration1
+FMC.MaxChipSelectPulse3=DISABLE
+FMC.WriteOperation1=FMC_WRITE_OPERATION_ENABLE
+FMC.WriteOperation2=FMC_WRITE_OPERATION_ENABLE
+FMC.WriteOperation3=FMC_WRITE_OPERATION_ENABLE
+FREERTOS.FootprintOK=true
+FREERTOS.IPParameters=Tasks01,FootprintOK
+FREERTOS.Tasks01=taskEPS,24,1024,taskEPSRunner,Default,NULL,Static,taskEPSBuffer,taskEPSControlBlock;taskSnap,48,1024,taskSnapRunner,Default,NULL,Static,taskSnapBuffer,taskSnapControlBlock;taskAI,24,37968,taskAIRunner,Default,NULL,Static,taskAIBuffer,taskAIControlBlock
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+I2C1.IPParameters=Timing
+I2C1.Timing=0x00707CBB
+I2C3.IPParameters=Timing
+I2C3.Timing=0x00707CBB
+KeepUserPlacement=false
+Mcu.CPN=STM32L552ZET3
+Mcu.ContextProject=TrustZoneDisabled
+Mcu.Family=STM32L5
+Mcu.IP0=ADC1
+Mcu.IP1=ADC2
+Mcu.IP10=NVIC
+Mcu.IP11=PWR
+Mcu.IP12=RCC
+Mcu.IP13=SPI1
+Mcu.IP14=SPI2
+Mcu.IP15=SYS
+Mcu.IP16=TIM7
+Mcu.IP17=UART4
+Mcu.IP18=USART1
+Mcu.IP19=USART2
+Mcu.IP2=DEBUG
+Mcu.IP20=USART3
+Mcu.IP21=USB
+Mcu.IP22=USB_DEVICE
+Mcu.IP3=FDCAN1
+Mcu.IP4=FMC
+Mcu.IP5=FREERTOS
+Mcu.IP6=GTZC
+Mcu.IP7=I2C1
+Mcu.IP8=I2C3
+Mcu.IP9=ICACHE
+Mcu.IPNb=23
+Mcu.Name=STM32L552ZETx
+Mcu.Package=LQFP144
+Mcu.Pin0=PE2
+Mcu.Pin1=PE3
+Mcu.Pin10=PF2
+Mcu.Pin100=PB8
+Mcu.Pin101=PB9
+Mcu.Pin102=PE0
+Mcu.Pin103=PE1
+Mcu.Pin104=VP_FREERTOS_VS_CMSIS_V2
+Mcu.Pin105=VP_GTZC_VS_GTZC_Enable
+Mcu.Pin106=VP_ICACHE_VS_ICACHE
+Mcu.Pin107=VP_PWR_VS_DBSignals
+Mcu.Pin108=VP_PWR_VS_SECSignals
+Mcu.Pin109=VP_SYS_VS_tim2
+Mcu.Pin11=PF3
+Mcu.Pin110=VP_TIM7_VS_ClockSourceINT
+Mcu.Pin111=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS
+Mcu.Pin12=PF4
+Mcu.Pin13=PF5
+Mcu.Pin14=PF6
+Mcu.Pin15=PF7
+Mcu.Pin16=PF8
+Mcu.Pin17=PF9
+Mcu.Pin18=PF10
+Mcu.Pin19=PH0-OSC_IN (PH0)
+Mcu.Pin2=PE4
+Mcu.Pin20=PH1-OSC_OUT (PH1)
+Mcu.Pin21=PC0
+Mcu.Pin22=PC1
+Mcu.Pin23=PC2
+Mcu.Pin24=PC3
+Mcu.Pin25=PA0
+Mcu.Pin26=PA1
+Mcu.Pin27=PA2
+Mcu.Pin28=PA3
+Mcu.Pin29=PA4
+Mcu.Pin3=PE5
+Mcu.Pin30=PA5
+Mcu.Pin31=PA6
+Mcu.Pin32=PA7
+Mcu.Pin33=PC4
+Mcu.Pin34=PC5
+Mcu.Pin35=PB0
+Mcu.Pin36=PB1
+Mcu.Pin37=PB2
+Mcu.Pin38=PF11
+Mcu.Pin39=PF12
+Mcu.Pin4=PE6
+Mcu.Pin40=PF13
+Mcu.Pin41=PF14
+Mcu.Pin42=PF15
+Mcu.Pin43=PG0
+Mcu.Pin44=PG1
+Mcu.Pin45=PE7
+Mcu.Pin46=PE8
+Mcu.Pin47=PE9
+Mcu.Pin48=PE10
+Mcu.Pin49=PE11
+Mcu.Pin5=PC13
+Mcu.Pin50=PE12
+Mcu.Pin51=PE13
+Mcu.Pin52=PE14
+Mcu.Pin53=PE15
+Mcu.Pin54=PB10
+Mcu.Pin55=PB12
+Mcu.Pin56=PB13
+Mcu.Pin57=PB14
+Mcu.Pin58=PB15
+Mcu.Pin59=PD8
+Mcu.Pin6=PC14-OSC32_IN (PC14)
+Mcu.Pin60=PD9
+Mcu.Pin61=PD10
+Mcu.Pin62=PD11
+Mcu.Pin63=PD12
+Mcu.Pin64=PD13
+Mcu.Pin65=PD14
+Mcu.Pin66=PD15
+Mcu.Pin67=PG2
+Mcu.Pin68=PG3
+Mcu.Pin69=PG4
+Mcu.Pin7=PC15-OSC32_OUT (PC15)
+Mcu.Pin70=PG5
+Mcu.Pin71=PG6
+Mcu.Pin72=PG7
+Mcu.Pin73=PG8
+Mcu.Pin74=PC6
+Mcu.Pin75=PC7
+Mcu.Pin76=PA8
+Mcu.Pin77=PA9
+Mcu.Pin78=PA10
+Mcu.Pin79=PA11
+Mcu.Pin8=PF0
+Mcu.Pin80=PA12
+Mcu.Pin81=PA13 (JTMS/SWDIO)
+Mcu.Pin82=PA14 (JTCK/SWCLK)
+Mcu.Pin83=PD0
+Mcu.Pin84=PD1
+Mcu.Pin85=PD2
+Mcu.Pin86=PD3
+Mcu.Pin87=PD4
+Mcu.Pin88=PD5
+Mcu.Pin89=PD7
+Mcu.Pin9=PF1
+Mcu.Pin90=PG9
+Mcu.Pin91=PG10
+Mcu.Pin92=PG11
+Mcu.Pin93=PG12
+Mcu.Pin94=PG13
+Mcu.Pin95=PG14
+Mcu.Pin96=PG15
+Mcu.Pin97=PB5
+Mcu.Pin98=PB6
+Mcu.Pin99=PB7
+Mcu.PinsNb=112
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32L552ZETx
+MxCube.Version=6.10.0
+MxDb.Version=DB.6.0.100
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.PendSV_IRQn=true\:7\:0\:false\:false\:false\:true\:false\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_3
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
+NVIC.SavedPendsvIrqHandlerGenerated=true
+NVIC.SavedSvcallIrqHandlerGenerated=true
+NVIC.SavedSystickIrqHandlerGenerated=true
+NVIC.SysTick_IRQn=true\:7\:0\:false\:false\:false\:true\:false\:true\:false
+NVIC.TIM2_IRQn=true\:7\:0\:false\:false\:true\:false\:false\:true\:true
+NVIC.TimeBase=TIM2_IRQn
+NVIC.TimeBaseIP=TIM2
+NVIC.USB_FS_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+PA0.GPIOParameters=GPIO_Speed
+PA0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA0.Mode=Asynchronous
+PA0.Signal=UART4_TX
+PA1.GPIOParameters=GPIO_Speed
+PA1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA1.Mode=Asynchronous
+PA1.Signal=UART4_RX
+PA10.GPIOParameters=GPIO_Speed
+PA10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA10.Mode=Asynchronous
+PA10.Signal=USART1_RX
+PA11.Mode=Device
+PA11.Signal=USB_DM
+PA12.Mode=Device
+PA12.Signal=USB_DP
+PA13\ (JTMS/SWDIO).Mode=Serial_Wire
+PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
+PA14\ (JTCK/SWCLK).Mode=Serial_Wire
+PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
+PA2.GPIOParameters=GPIO_Speed
+PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA2.Mode=Asynchronous
+PA2.Signal=USART2_TX
+PA3.GPIOParameters=GPIO_Speed
+PA3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA3.Mode=Asynchronous
+PA3.Signal=USART2_RX
+PA4.Locked=true
+PA4.Mode=NSS_Signal_Hard_Output
+PA4.Signal=SPI1_NSS
+PA5.Locked=true
+PA5.Mode=Full_Duplex_Master
+PA5.Signal=SPI1_SCK
+PA6.Locked=true
+PA6.Mode=Full_Duplex_Master
+PA6.Signal=SPI1_MISO
+PA7.Locked=true
+PA7.Signal=ADCx_IN12
+PA8.Locked=true
+PA8.Signal=GPIO_Output
+PA9.GPIOParameters=GPIO_Speed
+PA9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA9.Mode=Asynchronous
+PA9.Signal=USART1_TX
+PB0.Locked=true
+PB0.Signal=ADCx_IN15
+PB1.Locked=true
+PB1.Signal=ADCx_IN16
+PB10.GPIOParameters=GPIO_Speed
+PB10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB10.Locked=true
+PB10.Mode=Asynchronous
+PB10.Signal=USART3_TX
+PB12.Locked=true
+PB12.Mode=NSS_Signal_Hard_Output
+PB12.Signal=SPI2_NSS
+PB13.Locked=true
+PB13.Mode=Full_Duplex_Master
+PB13.Signal=SPI2_SCK
+PB14.Locked=true
+PB14.Mode=Full_Duplex_Master
+PB14.Signal=SPI2_MISO
+PB15.Locked=true
+PB15.Mode=Full_Duplex_Master
+PB15.Signal=SPI2_MOSI
+PB2.Locked=true
+PB2.Signal=GPIO_Output
+PB5.Locked=true
+PB5.Mode=Full_Duplex_Master
+PB5.Signal=SPI1_MOSI
+PB6.Locked=true
+PB6.Mode=I2C
+PB6.Signal=I2C1_SCL
+PB7.Locked=true
+PB7.Mode=I2C
+PB7.Signal=I2C1_SDA
+PB8.Locked=true
+PB8.Mode=FDCAN_Activate
+PB8.Signal=FDCAN1_RX
+PB9.Locked=true
+PB9.Mode=FDCAN_Activate
+PB9.Signal=FDCAN1_TX
+PC0.Locked=true
+PC0.Signal=ADCx_IN1
+PC1.Locked=true
+PC1.Signal=ADCx_IN2
+PC13.Locked=true
+PC13.Signal=GPIO_Output
+PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator
+PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN
+PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator
+PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT
+PC2.Locked=true
+PC2.Signal=ADCx_IN3
+PC3.Locked=true
+PC3.Signal=ADCx_IN4
+PC4.Locked=true
+PC4.Signal=ADCx_IN13
+PC5.GPIOParameters=GPIO_Speed
+PC5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PC5.Locked=true
+PC5.Mode=Asynchronous
+PC5.Signal=USART3_RX
+PC6.Locked=true
+PC6.Signal=GPIO_Output
+PC7.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PC7.GPIO_PuPd=GPIO_NOPULL
+PC7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PC7.Locked=true
+PC7.Signal=GPIO_Output
+PD0.Signal=FMC_D2_DA2
+PD1.Signal=FMC_D3_DA3
+PD10.Signal=FMC_D15_DA15
+PD11.Signal=FMC_A16_CLE
+PD12.Signal=FMC_A17_ALE
+PD13.Signal=FMC_A18
+PD14.Signal=FMC_D0_DA0
+PD15.Signal=FMC_D1_DA1
+PD2.Locked=true
+PD2.Signal=SDMMC1_CMD
+PD3.Locked=true
+PD3.Signal=GPIO_Output
+PD4.Signal=FMC_NOE
+PD5.Signal=FMC_NWE
+PD7.Mode=NorPsramChipSelect1_1
+PD7.Signal=FMC_NE1
+PD8.Signal=FMC_D13_DA13
+PD9.Signal=FMC_D14_DA14
+PE0.Signal=FMC_NBL0
+PE1.Signal=FMC_NBL1
+PE10.Signal=FMC_D7_DA7
+PE11.Signal=FMC_D8_DA8
+PE12.Signal=FMC_D9_DA9
+PE13.Signal=FMC_D10_DA10
+PE14.Signal=FMC_D11_DA11
+PE15.Signal=FMC_D12_DA12
+PE2.Signal=FMC_A23
+PE3.Signal=FMC_A19
+PE4.Signal=FMC_A20
+PE5.Signal=FMC_A21
+PE6.Signal=FMC_A22
+PE7.Signal=FMC_D4_DA4
+PE8.Signal=FMC_D5_DA5
+PE9.Signal=FMC_D6_DA6
+PF0.Signal=FMC_A0
+PF1.Signal=FMC_A1
+PF10.GPIOParameters=GPIO_PuPd
+PF10.GPIO_PuPd=GPIO_NOPULL
+PF10.Locked=true
+PF10.Signal=GPIO_Input
+PF11.GPIOParameters=GPIO_PuPd
+PF11.GPIO_PuPd=GPIO_NOPULL
+PF11.Locked=true
+PF11.Signal=GPIO_Output
+PF12.Signal=FMC_A6
+PF13.Signal=FMC_A7
+PF14.Signal=FMC_A8
+PF15.Signal=FMC_A9
+PF2.Signal=FMC_A2
+PF3.Signal=FMC_A3
+PF4.Signal=FMC_A4
+PF5.Signal=FMC_A5
+PF6.Locked=true
+PF6.Signal=GPIO_Output
+PF7.Locked=true
+PF7.Signal=GPIO_Output
+PF8.GPIOParameters=GPIO_PuPd
+PF8.GPIO_PuPd=GPIO_NOPULL
+PF8.Locked=true
+PF8.Signal=GPIO_Input
+PF9.GPIOParameters=GPIO_PuPd
+PF9.GPIO_PuPd=GPIO_NOPULL
+PF9.Locked=true
+PF9.Signal=GPIO_Input
+PG0.Signal=FMC_A10
+PG1.Signal=FMC_A11
+PG10.Mode=NorPsramChipSelect3_3
+PG10.Signal=FMC_NE3
+PG11.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PG11.GPIO_PuPd=GPIO_NOPULL
+PG11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PG11.Locked=true
+PG11.Signal=GPIO_Output
+PG12.Mode=NorPsramChipSelect4_4
+PG12.Signal=FMC_NE4
+PG13.Locked=true
+PG13.Signal=FMC_A24
+PG14.Locked=true
+PG14.Signal=FMC_A25
+PG15.Locked=true
+PG15.Signal=GPIO_Output
+PG2.Signal=FMC_A12
+PG3.Signal=FMC_A13
+PG4.Signal=FMC_A14
+PG5.Signal=FMC_A15
+PG6.Locked=true
+PG6.Signal=GPIO_Output
+PG7.Locked=true
+PG7.Mode=I2C
+PG7.Signal=I2C3_SCL
+PG8.Locked=true
+PG8.Mode=I2C
+PG8.Signal=I2C3_SDA
+PG9.Mode=NorPsramChipSelect2_2
+PG9.Signal=FMC_NE2
+PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
+PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
+PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
+PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32L552ZETx
+ProjectManager.FirmwarePackage=STM32Cube FW_L5 V1.5.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=STM32CubeIDE
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=imc_freertos_app_m33.ioc
+ProjectManager.ProjectName=imc_freertos_app_m33
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=STM32CubeIDE
+ProjectManager.ToolChainLocation=
+ProjectManager.UAScriptAfterPath=
+ProjectManager.UAScriptBeforePath=
+ProjectManager.UnderRoot=true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_FDCAN1_Init-FDCAN1-false-HAL-true,5-MX_FMC_Init-FMC-false-HAL-true,6-MX_I2C1_Init-I2C1-false-HAL-true,7-MX_I2C3_Init-I2C3-false-HAL-true,8-MX_SPI1_Init-SPI1-false-HAL-true,9-MX_SPI2_Init-SPI2-false-HAL-true,10-MX_TIM7_Init-TIM7-false-HAL-true,11-MX_UART4_Init-UART4-false-HAL-true,12-MX_USART1_UART_Init-USART1-false-HAL-true,13-MX_USART2_UART_Init-USART2-false-HAL-true,14-MX_USART3_UART_Init-USART3-false-HAL-true,15-MX_ICACHE_Init-ICACHE-false-HAL-true,16-MX_USB_Device_Init-USB_DEVICE-false-HAL-false,17-MX_GTZC_Init-GTZC-false-HAL-true,18-MX_ADC2_Init-ADC2-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true
+RCC.ADCFreq_Value=48000000
+RCC.AHBCLKDivider=RCC_SYSCLK_DIV2
+RCC.AHBFreq_Value=32000000
+RCC.APB1Freq_Value=32000000
+RCC.APB1TimFreq_Value=32000000
+RCC.APB2Freq_Value=32000000
+RCC.APB2TimFreq_Value=32000000
+RCC.CRSFreq_Value=48000000
+RCC.CortexFreq_Value=32000000
+RCC.DFSDMFreq_Value=32000000
+RCC.FCLKCortexFreq_Value=32000000
+RCC.FDCANFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=32000000
+RCC.HSE_VALUE=16000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=32000000
+RCC.I2C2Freq_Value=32000000
+RCC.I2C3Freq_Value=32000000
+RCC.I2C4Freq_Value=32000000
+RCC.IPParameters=ADCFreq_Value,AHBCLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,OCTOSPIMFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQ,PLLQoutputFreq_Value,PLLR,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value,WatchDogFreq_Value
+RCC.LPTIM1Freq_Value=32000000
+RCC.LPTIM2Freq_Value=32000000
+RCC.LPTIM3Freq_Value=32000000
+RCC.LPUART1Freq_Value=32000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=64000000
+RCC.MSI_VALUE=4000000
+RCC.OCTOSPIMFreq_Value=64000000
+RCC.PLLN=16
+RCC.PLLPoutputFreq_Value=36571428.571428575
+RCC.PLLQ=RCC_PLLQ_DIV4
+RCC.PLLQoutputFreq_Value=64000000
+RCC.PLLR=RCC_PLLR_DIV4
+RCC.PLLRCLKFreq_Value=64000000
+RCC.PLLSAI1N=24
+RCC.PLLSAI1PoutputFreq_Value=13714285.714285715
+RCC.PLLSAI1QoutputFreq_Value=48000000
+RCC.PLLSAI1RoutputFreq_Value=48000000
+RCC.PLLSAI2PoutputFreq_Value=4571428.571428572
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.PWRFreq_Value=64000000
+RCC.RNGFreq_Value=48000000
+RCC.RTCFreq_Value=32000
+RCC.SAI1Freq_Value=13714285.714285715
+RCC.SAI2Freq_Value=13714285.714285715
+RCC.SDMMCFreq_Value=36571428.571428575
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.UART4Freq_Value=32000000
+RCC.UART5Freq_Value=32000000
+RCC.USART1Freq_Value=32000000
+RCC.USART2Freq_Value=32000000
+RCC.USART3Freq_Value=32000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInput2Freq_Value=4000000
+RCC.VCOInput3Freq_Value=4000000
+RCC.VCOInputFreq_Value=16000000
+RCC.VCOOutputFreq_Value=256000000
+RCC.VCOSAI1OutputFreq_Value=96000000
+RCC.VCOSAI2OutputFreq_Value=32000000
+RCC.WatchDogFreq_Value=32000
+SH.ADCx_IN1.0=ADC1_IN1,IN1-Single-Ended
+SH.ADCx_IN1.ConfNb=1
+SH.ADCx_IN12.0=ADC1_IN12
+SH.ADCx_IN12.ConfNb=1
+SH.ADCx_IN13.0=ADC1_IN13
+SH.ADCx_IN13.ConfNb=1
+SH.ADCx_IN15.0=ADC1_IN15
+SH.ADCx_IN15.ConfNb=1
+SH.ADCx_IN16.0=ADC1_IN16
+SH.ADCx_IN16.ConfNb=1
+SH.ADCx_IN2.0=ADC1_IN2
+SH.ADCx_IN2.1=ADC2_IN2,IN2-Single-Ended
+SH.ADCx_IN2.ConfNb=2
+SH.ADCx_IN3.0=ADC1_IN3
+SH.ADCx_IN3.ConfNb=1
+SH.ADCx_IN4.0=ADC1_IN4
+SH.ADCx_IN4.ConfNb=1
+SH.FMC_A0.0=FMC_A0,24b-a2
+SH.FMC_A0.1=FMC_A0,21b-a1
+SH.FMC_A0.2=FMC_A0,20b-a3
+SH.FMC_A0.3=FMC_A0,20b-a4
+SH.FMC_A0.ConfNb=4
+SH.FMC_A1.0=FMC_A1,24b-a2
+SH.FMC_A1.1=FMC_A1,21b-a1
+SH.FMC_A1.2=FMC_A1,20b-a3
+SH.FMC_A1.3=FMC_A1,20b-a4
+SH.FMC_A1.ConfNb=4
+SH.FMC_A10.0=FMC_A10,24b-a2
+SH.FMC_A10.1=FMC_A10,21b-a1
+SH.FMC_A10.2=FMC_A10,20b-a3
+SH.FMC_A10.3=FMC_A10,20b-a4
+SH.FMC_A10.ConfNb=4
+SH.FMC_A11.0=FMC_A11,24b-a2
+SH.FMC_A11.1=FMC_A11,21b-a1
+SH.FMC_A11.2=FMC_A11,20b-a3
+SH.FMC_A11.3=FMC_A11,20b-a4
+SH.FMC_A11.ConfNb=4
+SH.FMC_A12.0=FMC_A12,24b-a2
+SH.FMC_A12.1=FMC_A12,21b-a1
+SH.FMC_A12.2=FMC_A12,20b-a3
+SH.FMC_A12.3=FMC_A12,20b-a4
+SH.FMC_A12.ConfNb=4
+SH.FMC_A13.0=FMC_A13,24b-a2
+SH.FMC_A13.1=FMC_A13,21b-a1
+SH.FMC_A13.2=FMC_A13,20b-a3
+SH.FMC_A13.3=FMC_A13,20b-a4
+SH.FMC_A13.ConfNb=4
+SH.FMC_A14.0=FMC_A14,24b-a2
+SH.FMC_A14.1=FMC_A14,21b-a1
+SH.FMC_A14.2=FMC_A14,20b-a3
+SH.FMC_A14.3=FMC_A14,20b-a4
+SH.FMC_A14.ConfNb=4
+SH.FMC_A15.0=FMC_A15,24b-a2
+SH.FMC_A15.1=FMC_A15,21b-a1
+SH.FMC_A15.2=FMC_A15,20b-a3
+SH.FMC_A15.3=FMC_A15,20b-a4
+SH.FMC_A15.ConfNb=4
+SH.FMC_A16_CLE.0=FMC_A16,24b-a2
+SH.FMC_A16_CLE.1=FMC_A16,21b-a1
+SH.FMC_A16_CLE.2=FMC_A16,20b-a3
+SH.FMC_A16_CLE.3=FMC_A16,20b-a4
+SH.FMC_A16_CLE.ConfNb=4
+SH.FMC_A17_ALE.0=FMC_A17,24b-a2
+SH.FMC_A17_ALE.1=FMC_A17,21b-a1
+SH.FMC_A17_ALE.2=FMC_A17,20b-a3
+SH.FMC_A17_ALE.3=FMC_A17,20b-a4
+SH.FMC_A17_ALE.ConfNb=4
+SH.FMC_A18.0=FMC_A18,24b-a2
+SH.FMC_A18.1=FMC_A18,21b-a1
+SH.FMC_A18.2=FMC_A18,20b-a3
+SH.FMC_A18.3=FMC_A18,20b-a4
+SH.FMC_A18.ConfNb=4
+SH.FMC_A19.0=FMC_A19,24b-a2
+SH.FMC_A19.1=FMC_A19,21b-a1
+SH.FMC_A19.2=FMC_A19,20b-a3
+SH.FMC_A19.3=FMC_A19,20b-a4
+SH.FMC_A19.ConfNb=4
+SH.FMC_A2.0=FMC_A2,24b-a2
+SH.FMC_A2.1=FMC_A2,21b-a1
+SH.FMC_A2.2=FMC_A2,20b-a3
+SH.FMC_A2.3=FMC_A2,20b-a4
+SH.FMC_A2.ConfNb=4
+SH.FMC_A20.0=FMC_A20,24b-a2
+SH.FMC_A20.1=FMC_A20,21b-a1
+SH.FMC_A20.ConfNb=2
+SH.FMC_A21.0=FMC_A21,24b-a2
+SH.FMC_A21.ConfNb=1
+SH.FMC_A22.0=FMC_A22,24b-a2
+SH.FMC_A22.ConfNb=1
+SH.FMC_A23.0=FMC_A23,24b-a2
+SH.FMC_A23.ConfNb=1
+SH.FMC_A24.0=FMC_A24
+SH.FMC_A24.ConfNb=1
+SH.FMC_A25.0=FMC_A25
+SH.FMC_A25.ConfNb=1
+SH.FMC_A3.0=FMC_A3,24b-a2
+SH.FMC_A3.1=FMC_A3,21b-a1
+SH.FMC_A3.2=FMC_A3,20b-a3
+SH.FMC_A3.3=FMC_A3,20b-a4
+SH.FMC_A3.ConfNb=4
+SH.FMC_A4.0=FMC_A4,24b-a2
+SH.FMC_A4.1=FMC_A4,21b-a1
+SH.FMC_A4.2=FMC_A4,20b-a3
+SH.FMC_A4.3=FMC_A4,20b-a4
+SH.FMC_A4.ConfNb=4
+SH.FMC_A5.0=FMC_A5,24b-a2
+SH.FMC_A5.1=FMC_A5,21b-a1
+SH.FMC_A5.2=FMC_A5,20b-a3
+SH.FMC_A5.3=FMC_A5,20b-a4
+SH.FMC_A5.ConfNb=4
+SH.FMC_A6.0=FMC_A6,24b-a2
+SH.FMC_A6.1=FMC_A6,21b-a1
+SH.FMC_A6.2=FMC_A6,20b-a3
+SH.FMC_A6.3=FMC_A6,20b-a4
+SH.FMC_A6.ConfNb=4
+SH.FMC_A7.0=FMC_A7,24b-a2
+SH.FMC_A7.1=FMC_A7,21b-a1
+SH.FMC_A7.2=FMC_A7,20b-a3
+SH.FMC_A7.3=FMC_A7,20b-a4
+SH.FMC_A7.ConfNb=4
+SH.FMC_A8.0=FMC_A8,24b-a2
+SH.FMC_A8.1=FMC_A8,21b-a1
+SH.FMC_A8.2=FMC_A8,20b-a3
+SH.FMC_A8.3=FMC_A8,20b-a4
+SH.FMC_A8.ConfNb=4
+SH.FMC_A9.0=FMC_A9,24b-a2
+SH.FMC_A9.1=FMC_A9,21b-a1
+SH.FMC_A9.2=FMC_A9,20b-a3
+SH.FMC_A9.3=FMC_A9,20b-a4
+SH.FMC_A9.ConfNb=4
+SH.FMC_D0_DA0.0=FMC_D0,16b-d1
+SH.FMC_D0_DA0.1=FMC_D0,16b-d2
+SH.FMC_D0_DA0.2=FMC_D0,16b-d3
+SH.FMC_D0_DA0.3=FMC_D0,16b-d4
+SH.FMC_D0_DA0.ConfNb=4
+SH.FMC_D10_DA10.0=FMC_D10,16b-d1
+SH.FMC_D10_DA10.1=FMC_D10,16b-d2
+SH.FMC_D10_DA10.2=FMC_D10,16b-d3
+SH.FMC_D10_DA10.3=FMC_D10,16b-d4
+SH.FMC_D10_DA10.ConfNb=4
+SH.FMC_D11_DA11.0=FMC_D11,16b-d1
+SH.FMC_D11_DA11.1=FMC_D11,16b-d2
+SH.FMC_D11_DA11.2=FMC_D11,16b-d3
+SH.FMC_D11_DA11.3=FMC_D11,16b-d4
+SH.FMC_D11_DA11.ConfNb=4
+SH.FMC_D12_DA12.0=FMC_D12,16b-d1
+SH.FMC_D12_DA12.1=FMC_D12,16b-d2
+SH.FMC_D12_DA12.2=FMC_D12,16b-d3
+SH.FMC_D12_DA12.3=FMC_D12,16b-d4
+SH.FMC_D12_DA12.ConfNb=4
+SH.FMC_D13_DA13.0=FMC_D13,16b-d1
+SH.FMC_D13_DA13.1=FMC_D13,16b-d2
+SH.FMC_D13_DA13.2=FMC_D13,16b-d3
+SH.FMC_D13_DA13.3=FMC_D13,16b-d4
+SH.FMC_D13_DA13.ConfNb=4
+SH.FMC_D14_DA14.0=FMC_D14,16b-d1
+SH.FMC_D14_DA14.1=FMC_D14,16b-d2
+SH.FMC_D14_DA14.2=FMC_D14,16b-d3
+SH.FMC_D14_DA14.3=FMC_D14,16b-d4
+SH.FMC_D14_DA14.ConfNb=4
+SH.FMC_D15_DA15.0=FMC_D15,16b-d1
+SH.FMC_D15_DA15.1=FMC_D15,16b-d2
+SH.FMC_D15_DA15.2=FMC_D15,16b-d3
+SH.FMC_D15_DA15.3=FMC_D15,16b-d4
+SH.FMC_D15_DA15.ConfNb=4
+SH.FMC_D1_DA1.0=FMC_D1,16b-d1
+SH.FMC_D1_DA1.1=FMC_D1,16b-d2
+SH.FMC_D1_DA1.2=FMC_D1,16b-d3
+SH.FMC_D1_DA1.3=FMC_D1,16b-d4
+SH.FMC_D1_DA1.ConfNb=4
+SH.FMC_D2_DA2.0=FMC_D2,16b-d1
+SH.FMC_D2_DA2.1=FMC_D2,16b-d2
+SH.FMC_D2_DA2.2=FMC_D2,16b-d3
+SH.FMC_D2_DA2.3=FMC_D2,16b-d4
+SH.FMC_D2_DA2.ConfNb=4
+SH.FMC_D3_DA3.0=FMC_D3,16b-d1
+SH.FMC_D3_DA3.1=FMC_D3,16b-d2
+SH.FMC_D3_DA3.2=FMC_D3,16b-d3
+SH.FMC_D3_DA3.3=FMC_D3,16b-d4
+SH.FMC_D3_DA3.ConfNb=4
+SH.FMC_D4_DA4.0=FMC_D4,16b-d1
+SH.FMC_D4_DA4.1=FMC_D4,16b-d2
+SH.FMC_D4_DA4.2=FMC_D4,16b-d3
+SH.FMC_D4_DA4.3=FMC_D4,16b-d4
+SH.FMC_D4_DA4.ConfNb=4
+SH.FMC_D5_DA5.0=FMC_D5,16b-d1
+SH.FMC_D5_DA5.1=FMC_D5,16b-d2
+SH.FMC_D5_DA5.2=FMC_D5,16b-d3
+SH.FMC_D5_DA5.3=FMC_D5,16b-d4
+SH.FMC_D5_DA5.ConfNb=4
+SH.FMC_D6_DA6.0=FMC_D6,16b-d1
+SH.FMC_D6_DA6.1=FMC_D6,16b-d2
+SH.FMC_D6_DA6.2=FMC_D6,16b-d3
+SH.FMC_D6_DA6.3=FMC_D6,16b-d4
+SH.FMC_D6_DA6.ConfNb=4
+SH.FMC_D7_DA7.0=FMC_D7,16b-d1
+SH.FMC_D7_DA7.1=FMC_D7,16b-d2
+SH.FMC_D7_DA7.2=FMC_D7,16b-d3
+SH.FMC_D7_DA7.3=FMC_D7,16b-d4
+SH.FMC_D7_DA7.ConfNb=4
+SH.FMC_D8_DA8.0=FMC_D8,16b-d1
+SH.FMC_D8_DA8.1=FMC_D8,16b-d2
+SH.FMC_D8_DA8.2=FMC_D8,16b-d3
+SH.FMC_D8_DA8.3=FMC_D8,16b-d4
+SH.FMC_D8_DA8.ConfNb=4
+SH.FMC_D9_DA9.0=FMC_D9,16b-d1
+SH.FMC_D9_DA9.1=FMC_D9,16b-d2
+SH.FMC_D9_DA9.2=FMC_D9,16b-d3
+SH.FMC_D9_DA9.3=FMC_D9,16b-d4
+SH.FMC_D9_DA9.ConfNb=4
+SH.FMC_NBL0.0=FMC_NBL0,2ByteEnable1
+SH.FMC_NBL0.1=FMC_NBL0,2ByteEnable2
+SH.FMC_NBL0.2=FMC_NBL0,2ByteEnable3
+SH.FMC_NBL0.3=FMC_NBL0,2ByteEnable4
+SH.FMC_NBL0.ConfNb=4
+SH.FMC_NBL1.0=FMC_NBL1,2ByteEnable1
+SH.FMC_NBL1.1=FMC_NBL1,2ByteEnable2
+SH.FMC_NBL1.2=FMC_NBL1,2ByteEnable3
+SH.FMC_NBL1.3=FMC_NBL1,2ByteEnable4
+SH.FMC_NBL1.ConfNb=4
+SH.FMC_NOE.0=FMC_NOE,Sram1
+SH.FMC_NOE.1=FMC_NOE,Sram2
+SH.FMC_NOE.2=FMC_NOE,Sram4
+SH.FMC_NOE.3=FMC_NOE,Psram3
+SH.FMC_NOE.ConfNb=4
+SH.FMC_NWE.0=FMC_NWE,Sram1
+SH.FMC_NWE.1=FMC_NWE,Sram2
+SH.FMC_NWE.2=FMC_NWE,Sram4
+SH.FMC_NWE.3=FMC_NWE,Psram3
+SH.FMC_NWE.ConfNb=4
+SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2
+SPI1.CalculateBaudRate=16.0 MBits/s
+SPI1.Direction=SPI_DIRECTION_2LINES
+SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS,BaudRatePrescaler
+SPI1.Mode=SPI_MODE_MASTER
+SPI1.VirtualNSS=VM_NSSHARD
+SPI1.VirtualType=VM_MASTER
+SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2
+SPI2.CalculateBaudRate=16.0 MBits/s
+SPI2.Direction=SPI_DIRECTION_2LINES
+SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS,BaudRatePrescaler
+SPI2.Mode=SPI_MODE_MASTER
+SPI2.VirtualNSS=VM_NSSHARD
+SPI2.VirtualType=VM_MASTER
+USART1.IPParameters=VirtualMode-Asynchronous
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+USART2.IPParameters=VirtualMode-Asynchronous
+USART2.VirtualMode-Asynchronous=VM_ASYNC
+USART3.IPParameters=VirtualMode-Asynchronous
+USART3.VirtualMode-Asynchronous=VM_ASYNC
+USB_DEVICE.CLASS_NAME_FS=CDC
+USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS
+USB_DEVICE.VirtualMode=Cdc
+USB_DEVICE.VirtualModeFS=Cdc_FS
+VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
+VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
+VP_GTZC_VS_GTZC_Enable.Mode=GTZC_Enable
+VP_GTZC_VS_GTZC_Enable.Signal=GTZC_VS_GTZC_Enable
+VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache
+VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE
+VP_PWR_VS_DBSignals.Mode=DisableDeadBatterySignals
+VP_PWR_VS_DBSignals.Signal=PWR_VS_DBSignals
+VP_PWR_VS_SECSignals.Mode=Security/Privilege
+VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals
+VP_SYS_VS_tim2.Mode=TIM2
+VP_SYS_VS_tim2.Signal=SYS_VS_tim2
+VP_TIM7_VS_ClockSourceINT.Mode=Enable_Timer
+VP_TIM7_VS_ClockSourceINT.Signal=TIM7_VS_ClockSourceINT
+VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS
+VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_FS
+board=custom
+rtos.0.ip=FREERTOS
+isbadioc=false