Update on local

sections/Introduction.tex

@@ -35,7 +35,7 @@ The major source of this discrepancy is the buffering effects of the system's in
 This factor has been overlooked in the traditional model, as the inherent capacitance was considered negligible compared to the main energy storage.
 
 Decoupling capacitors are on-board capacitors that act as energy buffers.
-They are mandatory components since the buffered energy prevent transient voltage drop when the system suddenly draws a large current, such as during checkpointing (Sec.~\ref{sec:system_description}).
+They are mandatory since the buffered energy prevent transient voltage drop when the system suddenly draws a large current, such as during checkpointing (Sec.~\ref{sec:system_description}).
 However, at the same time, their buffering effects introduce discrepancies between the execution model and the actual system behavior.
 For example, during power-on, decoupling capacitors are rapidly charged using the energy in the storage, making capacitor voltage an unreliable estimate of available energy.
 This buffered energy also allows the system operate for a while at sub-normal voltages after the power supply is stopped.

sections/OurApproach.tex

@@ -25,7 +25,7 @@ On the other hand, our model reveals that significant energy is wasted each time
 \begin{figure}
     \centering
     \includegraphics[width=\linewidth]{figs/plot_expr_7_cropped.pdf}
-    \caption{Execution times across various checkpoint voltages, normalized to the 3.4V case.}
+    \caption{Execution times across various checkpoint voltages, normalized to the 3.4V configuration.}
     \label{fig:expr_checkpoint_voltages}
 \end{figure}
 
@@ -93,8 +93,8 @@ The results clearly demonstrate that the execution time is significantly improve
 Furthermore, these improvements are consistent across all benchmarks, regardless of the application characteristics, highlighting the general effectiveness of the proposed setups.
 
 Another advantage of the proposed setups is their simplicity and practical applicability.
-Since the both setups only modify the method to detect imminent power failures and leave the checkpoint algorithms unchanged, it is straightforward to apply them in existing checkpoint techniques.
-Furthermore, the proposed setups can reduce the complexity of the system, as they eliminate the need for communication (e.g., interrupt or access to $V_{ES}$) between the energy storage system and the computing system.
+Since the both setups only modify the method to detect imminent power failures and leave the checkpoint algorithms unchanged, it is straightforward to apply them in existing techniques.
+Furthermore, the proposed setups can reduce the system complexity, as they eliminate the need for communication (e.g., interrupt or access to $V_{ES}$) between the energy storage system and the computing system.
 
 % \subsection{Checkpoint Techniques and Evaluation Methods}
 \subsection{On Selecting Hardware Components}

sections/OurModel.tex

@@ -30,9 +30,9 @@ In this context, we employ a custom-built board featuring a 32-bit ARM Cortex-M3
 For the power management system, we use a TI BQ25570-based board configured with $V_h$ = 4.9V and $V_l$ = 3.4V.
 % For the power management system, we use a TI BQ25570-based board with power-on and power-off thresholds of 4.9 V and 3.4 V, respectively.
 % A TI BQ25570 based board is used for the power management system, with power-on and off thresholds of 4.9V and 3.4V, respectively.
-We empirically select 22 uF and 220 uF capacitors for C1 and C2, respectively, as smaller capacitors fail to provide a reliable voltage for stable checkpoint and recovery.
+We empirically select 22uF and 220uF capacitors for C1 and C2, respectively, as smaller capacitors fail to provide a reliable voltage for checkpoint and recovery.
 % We empirically select 22uF and 220uF capacitors for C1 and C2, respectively, as these are the minimum capacitor sizes for stable checkpoint and recovery.
-Sec.~\ref{sec:other_architectures} evaluates the generality of our model across different architectures, such as systems with Magnetic RAM (MRAM) and a 16-bit core (e.g., MSP430).
+Sec.~\ref{sec:other_architectures} evaluates the generality of our model across different architectures, such as systems with different NVM (e.g., Magnetic RAM, MRAM) and a 16-bit core (e.g., MSP430).
 
 % In this work, our goal is to model the buffering effects of these capacitors and evaluate their implications on software designs.
 % (Recent studies present the need for better computing capability~\cite{bakarProtean2023a})
@@ -107,7 +107,8 @@ This indicates that much smaller energy may be used for the useful computation c
 \begin{figure}
     \centering
     \includegraphics[width=\linewidth]{figs/plot_expr_5_cropped.pdf}
-    \caption{Distribution of energy consumed in a power cycle in different capacitor sizes (1mA current supply).}
+    % \caption{Distribution of energy consumed in a power cycle in different capacitor sizes (1mA current supply).}
+    \caption{Distribution of energy consumed in a power cycle.}
     \label{fig:power_distribution}
 \end{figure}
 
@@ -176,10 +177,10 @@ This makes $V_{ES}$ not a reliable indicator for the imminent power-off.
 
 % Modern MCUs can operate on wide range of operating voltages (e.g., from 1.7V to 3.6V for STM32L5 and MSP430).
 
-Fig.~\ref{fig:sub_voltage_execution} presents the ratio of the times executed under sub-normal voltage to the total execution times, averaged over 30 measurements.
-The x-axis represents different capacitor sizes and the colors indicate the voltage levels at which the system stops operation.
+Fig.~\ref{fig:sub_voltage_execution} presents the ratio of the times executed under sub-normal voltages to the total execution times, averaged over 30 measurements.
+The x-axis represents capacitor sizes and the colors indicate the voltage levels at which the system stops operation.
 We evaluate a range of stop voltages from 1.7V to 2.5V since not all components in the computing system may function at the lowest voltage level (Sec.~\ref{sec:sub_normal_execution}).
-Also, we examine two cases with different input currents of 1 mA (Fig.~\ref{fig:sub_voltage_execution_1mA}) and 3 mA (Fig.~\ref{fig:sub_voltage_execution_3mA}), to assess the impact of input power.
+Also, we examine two cases with input currents of 1mA (Fig.~\ref{fig:sub_voltage_execution_1mA}) and 3mA (Fig.~\ref{fig:sub_voltage_execution_3mA}), to assess the impact of input power.
 
 The figure shows that a significant portion of MCU operation occurs at sub-normal voltages.
 For example, when 470uF capacitor is used at 1mA input current (Fig.~\ref{fig:sub_voltage_execution_1mA}), 82.8\% of computation takes place \emph{after} the power-off threshold.
@@ -220,7 +221,7 @@ At the same time, they are likely to operate at sub-normal voltages, as checkpoi
         \caption{External FRAM.}
         \label{fig:fram_drror}
     \end{subfigure}
-    \caption{Incorrectly functioning components at sub-normal voltage.} 
+    \caption{Incorrect operations at sub-normal voltages.} 
     \label{fig:adc_and_fram_error}
 \end{figure}
 

sections/RelatedWork.tex

@@ -7,7 +7,7 @@ Zhan et al.~\cite{zhanExploring2022} especially examined the trade-offs between
 However, these works assume that the entire energy discharged from the capacitor is utilized by computing system, overlooking the buffering effects addressed in this work.
 Furthermore, our work proposes several practical guidelines to improve the efficiency of existing techniques with minimal efforts.
 
-In some works that do not have a dedicated power management system and directly supply unregulated power to the computing system~\cite{balsamoHibernus2015,balsamoHibernus2016,netoDiCA2023,raffeckCO2CoDe2024,reymondEarlyBird2024}, the MCU operating voltage ($V_{dd}$) has been used as a checkpoint signal.
+In some works that do not have a dedicated power management system and directly supply unregulated power to the computing system~\cite{balsamoHibernus2015,balsamoHibernus2016,netoDiCA2023,raffeckCO2CoDe2024,reymondEarlyBird2024}, $V_{dd}$ has been used as a checkpoint signal.
 This is natural in these works since the voltage of the energy storage is always identical to $V_{dd}$.
 % This is natural in these works since the voltage of the energy storage is always same as Vdd and the MCU operates in varying voltage levels.
 In contrast, our work demonstrates that accounting for sub-normal voltage operation is also critical in systems with regulated power supplies, which represent the majority of intermittent system setups.