OurApproach.tex 1.1 KB

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  1. \section{Design Guidelines}
  2. \label{sec:design_guidelines}
  3. \subsection{Delay Checkpoint Execution}
  4. \begin{figure}
  5. \centering
  6. \includegraphics[width=\linewidth]{figs/plot_expr_7_cropped.pdf}
  7. \caption{Execution times across various checkpoint voltages, normalized to the 3.4V case.}
  8. % \label{fig:hardware_setup}
  9. \end{figure}
  10. \subsection{Use Vdd for Checkpoint Trigger}
  11. \begin{figure}
  12. \centering
  13. \begin{subfigure}{\linewidth}
  14. \includegraphics[width=\textwidth]{figs/plot_expr_10_cropped.pdf}
  15. \caption{Dynamic checkpointing (JIT).}
  16. % \label{fig:eval_voltage_trace}
  17. \vspace{7pt}
  18. \end{subfigure}
  19. \begin{subfigure}{\linewidth}
  20. \includegraphics[width=\textwidth]{figs/plot_expr_11_cropped.pdf}
  21. \caption{Static checkpointing.}
  22. % \label{fig:eval_adaptivenss_finished_tasks}
  23. \end{subfigure}
  24. \caption{Impact of precise checkpoint timings to the end-to-end execution times.}
  25. % \label{fig:sub_voltage_execution}
  26. \end{figure}
  27. \subsection{Design Checkpoint Techniques for Sufficient Power Duration}